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A Method and System for Adjusting a Data Strobe Signal Delay

IP.com Disclosure Number: IPCOM000216782D
Publication Date: 2012-Apr-19
Document File: 2 page(s) / 17K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for adjusting a data strobe signal delay for a Double Data Rate (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) is disclosed. The method and system enables writing a data pattern to a memory, reading the data pattern from the memory and determining an optimum delay line setting for each byte lane.

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A Method and System for Adjusting a Data Strobe Signal Delay

Disclosed is a method and system for adjusting a data strobe signal (DQS) delay for a Double Data Rate (DDR2) Synchronous Dynamic Random Access Memory (SDRAM).

The method and system performs a calibration process to adjust the delay of delay lines that correspond to the DQS strobe of the DDR2 SDRAM. The method consists of two parts: an automatic delay estimation circuit and state machine that runs continuously and a delay calibration circuit and state machine that runs once during system initialization. In a scenario, the delay lines may be implemented by connecting a number of delay blocks in series. The delay blocks may correspond to circuit blocks that provide a certain amount of delay to the delay lines. Additionally, various tap points along the delay block string are selected in order to select the desired amount of delay. The same kind of delay blocks may be used for the DQS delay lines and the automatic delay estimation circuit.

The automatic delay estimation circuit consists of a delay line long enough to achieve one clock cycle of delay under all conditions of voltage, temperature, and circuit variation. The state machine starts by setting the delay line tap to the minimum value and gradually increases the number of delay line taps until it determines the number of delay blocks needed to achieve one clock cycle of delay. The estimated delay value for the DQS delay lines is 1/4 of this value. The state machine runs continuously and periodically recomputes the estimated delay value.

The calibration process is performed by a sequential logic circuit, such as a state machine, that controls the DQS delay lines. In a scenario, the state machine performs the initialization sequence as described by a SDRAM manufacturer. Thereafter, the state machine writes a predetermined data pattern to the memory, wherein the predetermined data pattern may correspond to an incrementing sequence or a pseudo-random bit sequence.

After writing the data pattern to the memory, the state machine reads the predetermined data pattern from the memory. The state machine also regenerates the written data pattern and inputs the regenerated data pattern to the read logic for comparing the regenerated data pattern with the predetermined data pattern actually read from the m...