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Browse Prior Art Database

VSU/FXU powergating

IP.com Disclosure Number: IPCOM000216899D
Publication Date: 2012-Apr-23
Document File: 1 page(s) / 17K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for issuing instructions by a processor instruction set unit (ISU) while the execution unit is in a power saving mode is disclosed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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VSU/FXU powergating

Disclosed is a method for issuing instructions by a processor instruction sequencing unit (ISU) while the execution unit is in a power saving mode.

In previous power gating designs the ISU would not issue instructions to an execution unit until a power up handshake had completed. This handshake increased the amount of time spent between when the unit was ready to accept instructions and when they could actually be issued. With the existence of a post issue reject design, instructions are issued to the execution unit even if they are powered down. The power state is checked after the instruction is issued. In the event the unit was not ready, the instruction is rejected and reissued later. The initial issue also acts as a wake-up signal to the execution unit which limits the power gating interface signals to basically only a sub-unit ready pin.

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