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Improved FinFET spacer formation

IP.com Disclosure Number: IPCOM000217324D
Publication Date: 2012-May-07
Document File: 5 page(s) / 112K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an approach for fabricating a finFET with spacers on the gate sidewalls, without causing fin erosion. The inventive approach takes advantage of the substantial difference between gate pitch and fin pitch; gate pitch is much greater than fin pitch. A spacer material is deposited by a conformal deposition to partially fill the gate gap and completely fill the fin gap. A spacer is formed only on gate sidewall by performing a Reactive Ion Etching (RIE) process, which recesses the spacer material in fin gaps while forming spacers on the gate sidewalls.

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Improved FinFET spacer formation

FinFET has been touted as a viable device for continued Complementary Metal-Oxide Semiconductor (CMOS) scaling. A challenge for fabricating a finFET, due to the 3-D nature of finFET structure, is to form spacers on a gate sidewall without having spacers on the fin sidewall. The conventional spacer pull-down approach relies on an aggressive overetch which causes fin erosion.

This invention provides an inventive approach for forming spacers only on the gate sidewalls, without causing fin erosion. The inventive approach takes advantage of the substantial difference between gate pitch and fin pitch; gate pitch is much greater than fin pitch. A spacer material is deposited by a conformal deposition to partially fill the gate gap and completely fill the fin gap. A spacer is formed only on gate sidewall by performing a Reactive Ion Etching (RIE) process, which recesses the spacer material in fin gaps while forming spacers on the gate sidewalls.

The process flow for implementing the invention follows:

1. Form fins with a cap layer (e.g., oxide) on a semiconductor substrate (e.g., Semiconductor on Insulator (SOI))

Figure 1: In one embodiment, fin pitch (F1) is about 40nm, fin width (W1) is about 12nm, and space (S1) between fins is 28nm (S1 = F1 - W1)

2. Form gate by patterning (e.g., lithography) and etching (e.g., RIE). The gate may comprise a gate dielectric (e.g., high-k), gate conductor (e.g., metal), a gate hardmask (e.g., nitride)....