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A Smart Integrated Switch Cell for Well Bias Low Power Architecture

IP.com Disclosure Number: IPCOM000217634D
Publication Date: 2012-May-10
Document File: 4 page(s) / 433K

Publishing Venue

The IP.com Prior Art Database

Abstract

Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage. Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, cause their share of total power to increase. The identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. Today Low Power architectures target reducing leakage in various operating modes of the SoC. Well biasing is one of the techniques by which sub threshold leakage can be saved by raising the well potential of the chip in standby mode. Implementation of well biasing features require a high area/routing overhead due to PMOS switches spread across NWELL and supply in the sea of gates. This additional switching circuitry will result in area, power and routing overhead and may be meaningless in designs targeting small die area. Thus, there is a need of a cell with robust and uniform implementation technique that will overcome the limitations of well biasing.

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A Smart Integrated Switch Cell for Well Bias Low Power Architecture

Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage. Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, cause their share of total power to increase. The identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. Today Low Power architectures target reducing leakage in various operating modes of the SoC. Well biasing is one of the techniques by which sub threshold leakage can be saved by raising the well potential of the chip in standby mode. Implementation of well biasing features require a high area/routing overhead due to PMOS switches spread across NWELL and supply in the sea of gates. This additional switching circuitry will result in area, power and routing overhead and may be meaningless in designs targeting small die area. Thus, there is a need of a cell with robust and uniform implementation technique that will overcome the limitations of well biasing.

One known well biasing technique places a TIE cell and switching cell (level shifter) separately, but this consumes a large area. The technique assumes non-uniform manual placement of switch cell and TIE cell, which can lead to non-uniform well potential across the design and hence result in performance degradation such as timing and power, which can further lead to area increase.  This technique also assumes non-uniform routing of Enable Signal, which in lower technologies can hamper the performance of Switch cell itself due to RC parasitic and will waste routing resources, which can lead to routing congestion at SoC level. The methodology also is less robust because it connects the switch cells in a serial manner also known as daisy chain. If any point breaks down in the switch cell network, the whole well biasing will fail.  Therefore, we have developed a technique that does not suffer from this drawback as all the switch cells are connected in parallel across the die.

In this paper, an integrated Well Tap + PMOS Well Bias Switch is proposed, which results in reduced area overhead and robust routability of the design when implementing Well Bias architecture in the SoC. The following are the major advantages of the proposed technique in SoC:

Leakage :Our proposed integrated switch cell enabled the overall well biasing technique to be implemented, which can save leakage power during standby mode with very less impact on overa...