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Low power flop for limiting power in shift mode of an SoC

IP.com Disclosure Number: IPCOM000218102D
Publication Date: 2012-May-21
Document File: 4 page(s) / 258K

Publishing Venue

The IP.com Prior Art Database

Abstract

All SoCs use scan chains to detect manufacturing faults. Scan chains connect sequential elements of the chip in serial order. With more features being integrated in SoCs, the total number of flops (sequential elements) and combinational logic are increasing. During scan shift phase, peak power is a big concern because all flops along with combinational logic toggle during complete shift-in and shift-out phases and if peak power exceeds permissible limits, shift data may be corrupted causing a pseudo fail. In this paper we present a flop design that gates combinational logic toggling during shift phase, which reduces peak power.

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Low power flop for limiting power in shift mode of an SoC

 All SoCs use scan chains to detect manufacturing faults.  Scan chains connect sequential elements of the chip in serial order.  With more features being integrated in SoCs, the total number of flops (sequential elements) and combinational logic are increasing.  During scan shift phase, peak power is a big concern because all flops along with combinational logic toggle during complete shift-in and shift-out phases and if peak power exceeds permissible limits, shift data may be corrupted causing a pseudo fail.  In this paper we present a flop design that gates combinational logic toggling during shift phase, which reduces peak power.

Problem Description

A typical flip flop has two outputs, functional output (Q) and scan output (S0), which are shorted to each other.  A flop designer provides dedicated scan output for ease in hold timing closure in shift because in shift mode of SoC, scan output of flop is directly connected to scan input of the next flop in the scan chain and due to the absence of any combinational logic, this becomes hold timing critical.  In order to proactively avoid this problem, the designer provides a dedicated scan output, which is just a delayed version of functional output (Q).  As a result, during shift in and shift out phases, functional output Q along with scan output SO, continues to toggle depending upon scan input SI.  Since functional output Q toggles, all of the combinational logic also continues to toggle during complete shift in and shift out phases.  The above concept is illustrated in the below diagram.

Motivation to solve the problem:

It is very important to limit the power during shift.  The challenge is to limit power without affecting the design, instance count, and test time.  Currently, there are several means to achieve this like reducing shift frequency, creating multiple shift domains and then run them serially, limiting toggling during shift patter generation, etc.  However all these solutions affect test time and hence add to test cost.  

By stopping toggling of unnecessary combinational logic, peak power consumption during shift can be reduced significantly. 

One way to achieve this is to gate functional output during shift and ungate it during the capture cycle. Some work has been done in this area such that it is known to gate functional output with scan enable. In contrast, our idea is to hold functional output constant during shift as scan-enable will be 1 during shift and ungated in capture cycle so that capture happens on the latest value of scan-input and not on some old or constant value.

These circuits work fine for LOC (Launch on Capture) patterns but not for LOS (Launch on Shift) patterns because of huge constraint on timing.

LOS and LOC:  LOS and LOC are two flavors of at-speed testing.

LOC (Launch on capture)

In LOC, scan enable is made to fall after shift phase ends and then we have two capture pulses.  We c...