Adaptive Static Phase Error Compensation Engine for Charge Pump PLLs
Publication Date: 2012-Jun-01
The IP.com Prior Art Database
The disclosure describes Adaptive Static Phase Error Compensation Engine for Charge Pump PLLs
|Top Level PLL Architecture|
|Flow-chart of Operation|
|Advantages of the Proposed Design|
PFD1 and PFD2 is doing the same operation and can be merged for area and power savings
Top Level PLL Architecture
1.Static Phase Error Compensation (SPEC) engine is introduced to minimize static phase offset in DCPLF-PLL
2.The SPEC provides a control signal to the charge pumps, i.e., CP1 and CP2, to adjust the level of current propagating through the loop filter.
The proposed Static Phase Error Compensation (SPEC) engine includes:
|Difference Detector to determine lead-lag relationship between inp and inn|
|Voting Filter to accumulate lead-lag counts over a predetermined period and outputs the majority voting. In cases where the counts are same, hold state is asserted|
|Code Generator with optimizing algorithm to produce distinct code for each compensation magnitude|
The combination of these blocks produces ctrl signal as negative feedback to counteract the phase error
Flow-chart of Operation
The difference detector consists of an exclusive-OR gate to sense the phase difference between inp and inn
The delayed version of inp and inn pulses are used to sample the phase difference
The threshold for the allowable static phase error is programmable thru the delay cells.
The direction decoder controls the state of the bidirectional counters based on
|latest voting from voting filter|
|bidirectional counters’ existing count|
This block is implemented based on the novel algorithm (in the context of c...