Browse Prior Art Database

Adaptive Static Phase Error Compensation Engine for Charge Pump PLLs

IP.com Disclosure Number: IPCOM000218301D
Publication Date: 2012-Jun-01

Publishing Venue

The IP.com Prior Art Database

Abstract

The disclosure describes Adaptive Static Phase Error Compensation Engine for Charge Pump PLLs

This text was extracted from a Microsoft PowerPoint presentation.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Slide 1 of 12

Adaptive Static Phase Error Compensation Engine for Charge Pump PLLs


Slide 2 of 12

Contents

Background

Prior Art

Proposed Design

  Top Level PLL Architecture

  SPEC

  Flow-chart of Operation

  Architecture:

  Difference Detector

  Code Generator

  Advantages of the Proposed Design


Slide 3 of 12

Background

Conventional PLL facing an area bottleneck

due to a large area requirement for loop filter

Hence, a Dual Charge Pump Loop Filter PLL

is deployed to enable size shrinking

of loop filter. But, this solution causes big static phase error (SPE) due to mismatch between

charge pumps

[This slide contains 2 pictures or other non-text objects]


Slide 4 of 12

Prior Art : All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs Yong Liu, Woogeun Rhee, Daniel Friendman, Donhee Ham

PFD1 and PFD2 is doing the same operation and can be merged for area and power savings

[This slide contains 2 pictures or other non-text objects]


Slide 5 of 12

Proposed Design


Slide 6 of 12

Top Level PLL Architecture

1.Static Phase Error Compensation (SPEC) engine is introduced to minimize static phase offset in DCPLF-PLL

2.The SPEC provides a control signal to the charge pumps, i.e., CP1 and CP2, to adjust the level of current propagating through the loop filter.

[This slide contains 1 picture or other non-text object]


Slide 7 of 12

Static Phase Error Compensation (SPEC)

The proposed Static Phase Error Compensation (SPEC) engine includes:

  Difference Detector to determine lead-lag relationship between inp and inn

  Voting Filter to accumulate lead-lag counts over a predetermined period and outputs the majority voting. In cases where the counts are same, hold state is asserted

  Code Generator with optimizing algorithm to produce distinct code for each compensation magnitude

The combination of these blocks produces ctrl signal as negative feedback to counteract the phase error

[This slide contains 1 picture or other non-text object]


Slide 8 of 12

Flow-chart of Operation

[This slide contains 1 picture or other non-text object]


Slide 9 of 12

Difference Detector

The difference detector consists of an exclusive-OR gate to sense the phase difference between inp and inn

The delayed version of inp and inn pulses are used to sample the phase difference

The threshold for the allowable static phase error is programmable thru the delay cells.

[This slide contains 1 picture or other non-text object]


Slide 10 of 12

Code Generator

The direction decoder controls the state of the bidirectional counters based on

  latest voting from voting filter

  bidirectional counters’ existing count

This block is implemented based on the novel algorithm (in the context of c...