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METHODOLOGY FOR ROUTING CONSTRAINT DRIVEN CRITICAL SIGNALS IN CUSTOM IC LAYOUTS

IP.com Disclosure Number: IPCOM000220499D
Publication Date: 2012-Aug-02
Document File: 9 page(s) / 182K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel way of routing the critical signals of custom digital layouts by automatically detecting the critical nets and routing the signals automatically with priority and constraints. This significantly reuduces the overall cycle time of custom digital layouts with a quality of manualy done layout. Turn around time for ECOs are faster compared to the traditional method.

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METHODOLOGY FOR ROUTING CONSTRAINT DRIVEN CRITICAL SIGNALS IN CUSTOM IC LAYOUTS

    The current flow of routing the critical signals and clocks in custom digital macros are manual. The layout designer needs to go through the schematics and constraint for each and every signal user routes manually. The layout designer needs to understand the type of the signal and the criticality to come up with the shielding, spacing, length of the wire and proper width for the particular signal. The current problem with this approach is it requires lots of manual intervention.

And the routing done manually are highly error prone like LVS, DRC and the constraints. Fixing this errors in the layout after completion of the layout is very tedious.

    There are automation tools available to route the critical/clock signals still the tools needs lots of manual intervention and need to provide lots of data to the tool to come up the solution.


1. The routing of clocks and trunks are fully manual.


2. The present tool doesn't take care of the design rules and constraints completely.


3. The output from the LCR is not always clean. There could be shorts in the routed lines. It will be very hard to find, if there are shorts with power or ground signals.


4. Because of the manual approach, the selected track for routing the clocks may not be the optimal track for routing the particular clock and the might be occupied by other routings also.


5. After each and every routing the user needs to review the completed routings manually and it will be very tedious job to check the nets if the layout database is large.


6. If the naming conventions of the clocks nets are not followed, then the layout designer will not be able to identify that net as a clock and might skip that important clock net and will get routed by
the auto router. It will be very hard to change the layout once the routings are complete.


7. If the layout designer is not selecting the correct type of latch, then the present tool is not going to give the correct options for the particular latch type. Ex. Shielding of latch clocks will not be done,
if wrong latch type is selected in the present tool menu.


8. As most of the steps are manual it takes approximately 2 minutes per net to complete the routing. If the design with many internal clocks, the layout designer will spend most of the time in completing the clock routings.


9. The trunk lines are not in the optimal track location. In some cases the trunk routing utility cannot be used and the layout designer needs to complete them manually. The unwanted routings needs to be cleaned up manually.


10. The layout designer needs to give the metal layer to use to the tool.

Proposed Method :

In the proposed disclosure the Clock and Critical signals are automatically routed using the SKILL program.

-The program automatically detects the clock and critical signals and routes them

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automatically. ( Even if the net name patterns are not followed )

         -The routin...