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Method of Checking Performance of High Speed/Critical Interfaces in Mix Mode (RTL + Spice) AMS Simulations

IP.com Disclosure Number: IPCOM000220643D
Publication Date: 2012-Aug-09
Document File: 10 page(s) / 2M

Publishing Venue

The IP.com Prior Art Database

Abstract

The paper presents a complete process of running/checking performance of High Speed interfaces (GHz/DDR’s) in mixed mode (RTL + Spice) Analog Mixed Signal (AMS) verification. By inserting an abutted IO lump rail resistance in the RTL to account for the HS interfaces of interest, the performance (such as data signals eye openings or in other words the Data Valid Window) of these interfaces for a Plus/Minus lanes of the pads. This paper also presents a complex solution or methodology to achieve this goal.

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Method of Checking Performance of High Speed/Critical Interfaces in Mix Mode (RTL + Spice) AMS Simulations

Abstract : The paper presents a complete process of running/checking performance of High Speed interfaces (GHz/DDR’s) in mixed mode (RTL + Spice) Analog Mixed Signal (AMS) verification.  By inserting an abutted IO lump rail resistance in the RTL to account for the HS interfaces of interest, the performance (such as data signals eye openings or in other words the Data Valid Window) of these  interfaces for a Plus/Minus lanes of the pads.  This paper also presents a complex solution or methodology to achieve this goal.

Contents

i)        Motivation of Analysis (What is the target?)  

a.       Companies are running standalone Spice simulations for DDR or high speed interfaces to calculate SSN jitter numbers, etc.  However, never focusing on performance of these interfaces with respect to real use cases/verification patterns in mixed mode (RTL + Spice) simulations.

b.      Even high speed interfaces currently are not being verified in mixed mode (RTL + Spice) simulations that are close to post Silicon data/results.

c.       Due to SoC ball limitations, SoCs are designed with many functional pads tied to Power/Ground so that the pad ratio of the overall performance of the two high speed interfaces on the same power can inject noise as well as degrade the results the interfaces.

ii)      Motivation to Solve/Break the trend

a.        To define/verify a new methodology to cater to the pad ring IR drop within the mixed mode simulations to capture the performance/degradation of these high speed data signals.

b.      Automatically insert pad ring rail resistance in RTL so that it doesn’t impact the pure RTL based SoC Verification.

c.       Based on AMS simulations, you capture many of the AC timing specification ( DVW, Attenuation  /supply ripple due to high speed pad switching to the adjacent IO’s ) at the  mixed mode simulations.

d.      A totally new methodology where we can check/run performance of these high speed interfaces, which is closer to replicating the real use case of the SoC.

iii)    Where do we start?

Define the following new methodology for pure mixed mode SoC Verification

a)      Define precise standard inputs requirements for automation of methodology

b)      Define a flow chart and develop the scripts for automation

c)       Take a test case to verify the new methodology

d)      Run three sets of mixed mode (RTL + Spice simulations)

i)                    Pure RTL (Standard)

ii)                   Pure RTL (New : with rail resistance < to cater IR drop for Padring> in RTL)

iii)                 Pure RTL (New : with rail resistance <to cater IR drop for Padring> in Spice)

e)      Results comparison with respect to performance of the high speed interfaces from the above three sets of simulations

f)       Conclusion with the observation along with some side notes

iv)    What are the inputs required for this new methodology?

Below is the list of inputs required to implement this methodology.

a)      Structural Padring RTL ( with very fixed standard format )

b)      Pads/...