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Mixed Signal Verification Method of Sigma Delta ADC

IP.com Disclosure Number: IPCOM000221585D
Publication Date: 2012-Sep-12
Document File: 10 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper presents a parameterized Verilog-AMS SNR/ENOB and Dynamic Range calculator that can be used to test different ADC architectures (SAR, SD-ADC). The data from these VAMS models have been compared against MATLAB for correlation. This paper also contains Mixed Signal Verification methods for ADC dynamic tests where a simple formula can be applied to any ADC subsystem to calculate the Signal and the Noise Frequency. Using this method one can do noise rejection checks, see the clock jitter impact on SNR across different SoC modes of operation (PLL, IRC, etc.), perform Dynamic Range Check through VAMS monitor to identify signal attenuation due to bad IO muxing, high source impedance, and sampling issues at high clock speeds.

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Mixed Signal Verification Method of Sigma Delta ADC

Abstract:  This paper presents a parameterized Verilog-AMS SNR/ENOB and Dynamic Range calculator that can be used to test different ADC architectures (SAR, SD-ADC). The data from these VAMS models have been compared against MATLAB for correlation. This paper also contains Mixed Signal Verification methods for ADC dynamic tests where a simple formula can be applied to any ADC subsystem to calculate the Signal and the Noise Frequency.  Using this method one can do noise rejection checks, see the clock jitter impact on SNR across different SoC modes of operation (PLL, IRC, etc.), perform Dynamic Range Check through VAMS monitor to identify signal attenuation due to bad IO muxing, high source impedance, and sampling issues at high clock speeds.

Contents

Motivation for this method

Dynamic checks for data converters are done at the post Silicon phase, where the dynamic parameters are calculated. These parameters, if have a lower value than expected, can easily be used to determine which blocks in a Data Converter Subsystem are the culprits.  One of the main motivations was that the dynamic checks for data converters be done and issues identified early in the pre-Silicon simulation phase itself.

The impact of noise on input can be checked and data converter characteristics can be estimated against poor signal quality.  The impact of clock jitter can be verified in the simulations to measure impact in SNDR/SNR.  A VAMS based model for SNDR/SNR calculation eliminates MATLAB usage, which is also encouraged due to licensing and cost reasons.  Also, data need not be manually entered as the VAMS model collects the data when included in the test bench.  This is not possible in MATLAB for analysis, i.e. the proposed flow works simultaneously with data collection without MATLAB.

Problems this method can solve

Traditional verification methods do not detect parametric like SNR/ENOB and rely purely on digital/analog measurement accuracy.  The proposed method and flow solves this problem by giving a calculated stimulus that not only tests the modulator (in case of Sigma Delta ADC), but also tests the performance of the decimation filter.  ADC dynamic characteristics are crucial for many markets e.g. metering, motor control, etc.  Presently, SoC teams rarely check these with SoC network of data converter and its IO/muxing interface.

MATLAB is a standard tool used to perform the analysis to determine dynamic performance, but licensing cost is a concern.  Our proposed flow not only eliminates the usage of MATLAB but eases the calculation of the dynamic parameters.  It also performs noise rejection/tolerance, which is not checked in pure digital verification.

Design Solution – VAMS SNR Monitor

A parameterized VAMS model described in the flow chart shown in Figure 1 contains 4 inputs – Signal Frequency, Sampling Frequency, Number of Samples (N) and No. of bits in the ADC output. When this model is in...