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An efficient Voltage / Power Attribute based low power functional verification technique

IP.com Disclosure Number: IPCOM000222906D
Publication Date: 2012-Oct-29
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Background:

This document is related to functional verification of low power designs. Various limitations related to traditional functional verification exists when verifying low power designs, these limitations are related to discrepancies on power gating cells and their hook ups which traditional verification does not comprehend.

Hence a need arise on low power verification that could comprehend anomalies pertaining to low power gating cells and their hookups. These involve missing / incorrect usage of power gating cells (isolation, logic retention, level shifters).

Across industry, low power verification is performed by utilizing power format files (UPF, CPF) applied to RTL / non PG netlist, or by modeling supply and ground on every gate primitive.

Various other low power techniques such as Static Multi voltage Rule checks with power format support are available in the industry but they do not currently comprehend the low power dynamic changes of functionality and hence corner cases exists which makes it a mandate to perform Power Aware functional simulations on low power designs.

Also the primitive models built currently face technical challenges of increased verification database size and simulation run time due to complex modeling involving supply and ground to gate primitives / modules.

Mixed signal Sims could also be used to catch these issues, but these would be very expensive and heavily time consuming and might not hit all corner cases.

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An efficient Voltage / Power Attribute based low power functional verification technique

Summary:

The proposed technique comprehends the above stated issue pertaining to technical challenges of simulation run time and verification database size by attaching an attribute / attributes, based on supply source to the pins of each primitive gate / logic module. These attributes could be in the form of an alphanumeric character corresponding to every voltage / power source.

Power gating cells would be handled by having multiple attributes to individual pins.

A mismatch in attributes on a net at an event / cycle (for event / cycle based simulators) would be flagged as unexpected simulation behavior.

An attribute collapsing technique could be implemented when a verification database is built based on cells having same attribute for driving / driven nets with exceptions to power gating cells.

Description:

RTL simulations / Gate Sims (without supply/ground modeling) depend on power format files during logic simulations, These power format files today across EDA tools are also used for synthesis physical design and other chip implementation aspects. Common usage across these

power format files could lead to inaccurate / incorrect logic verification.

When power / ground modeled netlist is used, It involves a significant overhead of modeling supply and ground on every gate primitive model which slows the simulation due to overhead of these signals being induced further to this, this also would...