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Method of AC scan design implementation for reduction of current load spikes

IP.com Disclosure Number: IPCOM000223134D
Publication Date: 2012-Nov-05
Document File: 3 page(s) / 174K

Publishing Venue

The IP.com Prior Art Database

Abstract

• AC scan testing is done in a similar way to DC scan with one critical difference – after all data is shifted into FF’s, the launch and capture cycles are done at real frequency, that should be tested. • It’s done by moving clock source for launch and capture cycles to clock generator, while clock for shift phase is done with external clock. • Shift frequency is usually pretty small (below 100Mhz), due to many lock-up latches, placed between different frequency domains and stitching between chains placed far apart. • Another reason for low shift frequency is limitation of IO cells, since data is driven from outside of the chip.

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Method of AC scan design implementation for reduction of current load spikes

Abstract

·         AC scan testing is done in a similar way to DC scan with one critical difference – after all data is shifted into FF’s, the launch and capture cycles are done at real frequency, that should be tested.

·         It’s done by moving clock source for launch and capture cycles to clock generator, while clock for shift phase is done with external clock.

·         Shift frequency is usually pretty small (below 100Mhz), due to many lock-up latches, placed between different frequency domains and stitching between chains placed far apart.

·         Another reason for low shift frequency is limitation of IO cells, since data is driven from outside of the chip.

Introduction

  • AC scan pattern has high active cells percentage during launch and capture cycles, that results in high current consumption during these cycles. If activity percentage is aligned with usual activity percentage during functional tests, IR drop, caused by this current should be no problem.
  • The problem is the sharp change of above current .
  • Inductance parasitic of package cause high voltage ripple, that doesn’t allow high speed testing

Fig. 1 demonstrates the scenario, when at speed cycles causing high current spikes.

                                                             Fig. 1

Proposed solution

  • The proposal is to build an optimized pattern of shift phase frequency to reduce cur...