Browse Prior Art Database

Liquid-Cooled Matrix Packaging Utilizing Low Latency Vertical Interconnect for Processor-Memory Data Flow

IP.com Disclosure Number: IPCOM000223173D
Publication Date: 2012-Nov-06
Document File: 5 page(s) / 143K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a novel method for interconnecting integrated circuit (IC) modules. The intent is to integrate a matrix of liquid-cooled members interspersed with processor and memory modules. This architecture will also yield low latency connections between the ICs and reduce unintended radiated electromagnetic energy due to the shorter interconnections and fewer signal transitions.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 5

Liquid-

-Cooled Matrix Packaging Utilizing Low Latency Vertical Interconnect for

    Cooled Matrix Packaging Utilizing Low Latency Vertical Interconnect for Processor-

-Memory Data Flow

Memory Data Flow

Always needed is a quicker path in the interconnection of processors and nearby memory. The fewer signal mismatches the better. Every change of permittivity represents a slight bump in impedance. Minimizing the distance is also of importance.

    Discussed here is a structure that alters the processor module packaging to provide data interconnection columns at each corner. By raising the corners above the typical packaging, an interconnection between support chips may be made using one transition. Both memory and processor modules contain eight ports. Raising the columns allows spacing between the columns for cooling and lower speed, power, and cooling.

    Shown in Figure 1 below is the processor packaging that shows a four-column, eight-port interconnect designed into the packaging structure. By having the columns perform the interconnect, a high-speed connection to another medium (FR4) is avoided along with its mismatch and impedance change. The column interconnects can consist of alignment pins, metallic contacts, and/or optical ports.

    Also, by having the columns perform the interconnect, water-based cooling and low-speed FR4 interconnects can surround the columns. The circuit board and cooling will have through hole ports for the column interconnects, but the processor module will have the only Z axis protrusions allowing the remaining packaging to remain essentially two dimensional. The center section of the module package is thinner to allow a low thermal resistance between the internal chips and the cooling block. For supercomputing, the configuration is highly structured, meaning the heights of the processor and memory modules are tightly controlled to allow the three-dimensional matrix to function. So, if a mix of chips is needed, the cooling structure would need to be designed to account for varied heights of the modules requiring a custom design. For this scheme, the heights of the processors and memory is fixed to for...