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AGI Bypass Stack For Early Resolution

IP.com Disclosure Number: IPCOM000223237D
Publication Date: 2012-Nov-12
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

A new Address Generation Interlock (AGI) stack, called the AGI bypass stack, provides for early resolution for interlocks caused by certain instructions such as LOAD ADDRESS instructions, BRANCH on INDEX, LINKING BRANCHES and LOAD instructions.

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AGI Bypass Stack For Early Resolution

Under certain circumstances, the pipeline address generation (AGEN) stage, which needs to read general registers (GRs) as inputs to address generation, may be stalled until the architecturally correct values for the GRs can be read. This stall is commonly referred to as an Address Generation Interlock (AGI) condition.

Some instructions update a GR without altering the data from the source. For example, a LOAD simply obtains data from storage and places it in a GR. Since the Instruction unit (I-unit) has access to some of these sources, it is possible for the I-unit to monitor these sources, save the information and associate this information (future GR contents) with the corresponding instruction, which is pending execution. Such information is saved in the AGI bypass stack. If at a later time, it is discovered such an instruction is the cause of an AGI condition, the future contents for the GR of interest can be obtained from the AGI bypass stack and AGEN can be performed without waiting for the Execution unit (E-unit) to execute the instruction causing the AGI condition (performance enhancement). This is referred to as AGI early resolution.

Early resolution is accomplished for interlocks caused by LOAD ADDRESS instructions via instruction queue (I-queue) address registers. As a result of improvements made to I-queues (by, for example, making them deeper), a new AGI bypass stack was invented.

Disclosed is an AGI bypass stack that comprises three 64-bit entries. A new entry may be obtained from the address adder, instruction address or D-cache (an indexed cache that stores a large amount of data). An entry in the AGI bypass stack can be provided as input to either AGEN registers (i.e. the base or index registers). Associated with each entry is the instruction type, register destination, instruction ID, state and valid bits. AGI bypass stack entries correspond to the most recent updates with respect to instruction decoding.

Figure 1

Adding and removing AGI bypass stack entries :


As each instruction decodes, it is determined whether or not the instruction updates GRs or ARs and if so, which GR(s) or AR(s). If a match exists between the GR to be updated by the instruction decoding and

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an AGI bypass stack entry, then the stack entry is invalidated (the current stack entry is no longer the most recent update). If the instruction being decoded is in the set of qualifying instructions (ie. LA, BXLE, BALR, L, etc.), an AGI bypass stack entry is assigned. The entry is not valid for early resolution until the corresponding data can be captured, which depends on the type of instruction causing the entry. An entry is not removed, even after the corresponding instruction has...