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Self-planarization process for gate cap nitride removal

IP.com Disclosure Number: IPCOM000223272D
Publication Date: 2012-Nov-15
Document File: 3 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a self-planarization process for gate cap nitride removal

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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Self-planarization process for gate cap nitride removal

There is severe nitride spacer pulldown during gate nitride cap removal due to different nitride cap thickness in NFET, PFET and N/P transition region.

Nitride (SiN) cap on gate (PC) has been widely used to protect gate during selective epitraxy processes inside source/drain (S/D) of Field Effect Transistors (FETs). Uneven nitride thicknesses on gate contribute to a large non-uniformity during nitride removal process, which is necessary for silicide formation or replacement metal gate (RMG) technique. A controlled removal using Reactive Ion Etching (RIE) can be achieved with the use of self-planarizing organic material such as ODL/OPL or ARC that are normally used in lithography. Process uniformity can be further improved by adjusting or controlling selectivity in RIE process.

Figure 1: Representation of the problem

This invention uses self-planarizing ODL (or ARC) and non-selective RIE to eliminate severe spacer pulldown driven by different cap nitride thickness.

Figure 2: Process Flow 1: After N & P S/D formation

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Figure 3: Process Flow 2: Coat self-planarization ODL or ARC

Figure 4: Process Flow 3: Non selective etch (ODL/ARC vs SiN)

Figure 5: Process Flow 4:


• Strip ODL (or ARC)


• Silicide pre-clean


• Silicidation


• etc.

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