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A Nanowire eDRAM Structure and Method with Metal-Insulator-Metal Capacitors (MIMCAP) and Transmission Gates for Cell Access

IP.com Disclosure Number: IPCOM000223285D
Publication Date: 2012-Nov-15
Document File: 1 page(s) / 50K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a nanowire EDRAM cell/array, re-using the pad region to form metal-insulator-metal capacitors (MIMCAPs) and using the devices between the pads to form the access gates.

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A Nanowire eDRAM Structure and Method with Metal -Insulator-Metal Capacitors (MIMCAP) and Transmission Gates for Cell Access

Disclosed is a nanowire eDRAM structure which places the eDRAM MIM capacitor in the pad region used to suspend the nanowire FETs.

Figure illustrates an eDRAM structure where the pad regions are reused for trench capacitor.

Figure

As illustrated, between the pads alternate columns of two NFET and two PFET nanowire FET devices are placed. Every MIMCAP region is therefore contacted by one nanowire NFET device and one nanowire PFET device, which thus forms a transmission gate to access the storage capacitor.

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