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An On-chip MOSFET Breakdown Process Prognostics Circuit and Reliability Sensor

IP.com Disclosure Number: IPCOM000223290D
Publication Date: 2012-Nov-15
Document File: 5 page(s) / 147K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a new method of improving the chip reliability, which provides reliability in a deterministic (not statistic) value for each individual chip. The approach is to monitor device reliability by implementing a mini on-chip real-time reliability stress on a reliability sensor circuit during a chip’s operational lifetime. Reliability sensors are SRAM-like with four individual blocks. The leading breakdown failure mechanism can be identified.

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An On-chip MOSFET Breakdown Process Prognostics Circuit and Reliability Sensor

For current state-of-the-art integrated circuits (ICs), reliability is rapidly becoming one of the greatest challenges for technology development. A single chip reliability failure can cause an entire chip or system failure. With the continued scaling of Very Large Scale Integration (VLSI) circuits, reliability margins for all wearout mechanisms are shrinking. This is particularly true for medical, automobile and military applications, which require early- stage indicators for each individual chip.

Gate sidewall dielectric breakdown and Gate-to-diffusion dielectric breakdown coexist and compete during chip operation. A single early reliability failure determines the whole chip reliability. Due to the statistic nature (billions of transistors and >10m long total interconnect segments), a small-area sensor circuit cannot guarantee that no single device or interconnect segment from the whole chip will fail earlier than sensor. Therefore, the whole idea loses credibility if one device/interconnect segment causes chip failure earlier than the small-area sensor detects a problem.

Currently, no known solutions exist for on-chip, real-time reliability prognostics. Prognostics is a method that allows one to monitor the state of reliability of a chip in real time, and therefore provide advance warning of failure.

On the other hand, the minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. Static Random-Access Memory (SRAM) yield loss and functional stress failures of both SRAM and Dynamic Random-Access Memory (DRAM) chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, there is a need to design an on-chip sensor to monitor PC-CA reliability status specifically.

A monitor is needed that covers both failure mechanisms and simultaneously monitors them.

The solution is to monitor device reliability by implementing a mini on-chip real-...