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A method and structure to find a defective element in 3D FPGA

IP.com Disclosure Number: IPCOM000223291D
Publication Date: 2012-Nov-15
Document File: 3 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are the architecture and the testing procedures to enable the defect diagnosis for individual logic elements, routing switches and wires, and the Through Silicon Vias (TSVs) during the manufacturing of 3D Field-Programmable Gate Arrays (FPGAs).

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A method and structure to find a defective element in 3D FPGA

A fault-tolerant design is a potentially key enabler to reduce the manufacturing cost of 3D Field-Programmable Gate Arrays (FPGAs). In 3D wafer-to-wafer stacking technology, the dies cannot be sorted before stacking. To achieve fault-tolerance, testing is required to define the defective elements. As the faulty parts are identified, the FPGA mapping flow avoids using the defective elements while configuring the FPGA into a user-specified function using the fault-free part.

The vertical connections in 3D FPGAs provide more routing flexibility compared to conventional 2D FPGAs. As at least a fault exists in one stratum, the faulty data-paths can be rerouted using wires in other strata to bypass the faults.

The presented architecture and the testing procedures enable the defect diagnosis for individual logic elements, routing switches and wires, and the Through Silicon Vias (TSVs). The 3D FPGA architecture contains island-style logic blocks (LBs), which perform logic computations. LBs are connected by wire segments in the routing channel. Switch blocks (SBs) connect the wire segments, while the connection blocks (CBs) connect the input and output ports of each LB to the interconnection network. In the user mode, the inputs to the LBs are provided by the interconnect network. In the testing mode, data inputs can be applied to one specific LB. In addition, the logic output of another specific LB can be observed externally through an output pin. To control the FPGA, scan chains are used to store the configuration bits. TSVs are inserted among the logic fabric to support vertical communications.

Figure 1 summarizes the testing flow for the FPGA architecture. First, since the function of an FPGA relies on the correct configuration, the scan-in latches for configuration bits should be tested.

Figure 1: Testing flow

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