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A method of correcting Through Silicon Via (TSV) regions

IP.com Disclosure Number: IPCOM000223372D
Publication Date: 2012-Nov-20
Document File: 2 page(s) / 68K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method of correcting Through Silicon Via (TSV) regions of integrated circuits is disclosed. Damaged TSV regions of integrated circuits are corrected to ensure that the TSV regions meet desired specifications.

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Page 01 of 2

A method of correcting Through Silicon Via (TSV) regions

It is essential for a geometric profile of a Through Silicon Via (TSV) to meet desired specifications. A desired specification of a TSV sidewall may be a vertical profile. Variations in the profile of the sidewall may affect process such as isolation liner process, TSV fill and planarization. Non conformity to geometrical specifications may also cause an undesirable shorting between adjacent TSVs. Non conformity to geometrical specifications may be due to excessive mask erosion during an etching process. The excessive mask erosion may also cause a TSV region to be flared or damaged. Disclosed is a method of correcting damaged TSV regions of integrated circuits.

In an exemplary embodiment, a damaged sidewall of an etched TSV region of an integrated circuit is corrected. The damaged sidewall may be as illustrated in fig.1.

Figure 1

1


Page 02 of 2

Figure 2

The damaged TSV region may be corrected by a deposition of a non-conformal dielectric film over the damaged sidewall. The non-conformal dielectric film may be deposited during an etching process such that the dielectric film is formed over a damaged corner of the sidewall of the TSV region as seen in fig. 2. A non limiting example of a dielectric film deposition may include Plasma-Enhanced Chemical Vapor Deposition (PECVD) of Silicon Dioxide using Tetra ethyl ortho silicate (TEOS). The deposition of the dielectric film may aid in maintaining a vertical prof...