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Structure and Method to modulate Vt using STI liner

IP.com Disclosure Number: IPCOM000223377D
Publication Date: 2012-Nov-20
Document File: 2 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel approach to maintain good performance in high-k gate stacks by controllably delivering oxygen only to the Positive Channel Field Effect Transistor (PFET) device and not the Negative Channel (N) FET when introducing oxygen in the gate dielectric. The method incorporates a high-k Shallow Trench Isolation (STI) liner as a conduit for oxygen diffusion and linking it to the gate dielectric only for the PFET.

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Structure and Method to modulate Vt using STI liner

Advanced high-k gate stacks used in nanoscale devices do not provide symmetric Vts for n-Channel Metal Oxide Semiconductor (NMOS) and p-channel Metal Oxide Semiconductor (PMOS) leading to poor performance.

It is common knowledge that the introduction of oxygen in the gate dielectric reduces oxygen vacancies and decreases Positive Channel Field Effect Transistor (PFET) Vt. The challenge has been to controllably deliver this oxygen only to the PFET device and not the Negative Channel (N) FET.

Disclosed is a novel approach to achieving this by using a high-k Shallow Trench Isolation (STI) liner as a conduit for oxygen diffusion and linking it to the gate dielectric only for the PFET.

The STI liner makes contact with the gate dielectric at the RX-PC interface. By using an HfO2 or HfSiOx STI liner, the approach enables the transport of oxygen from the STI to the gate dielectric. In the regions where oxygen transport is not wanted, the approach either skips the HfO2 liner or prevents the liner/gate dielectric overlap using an oxygen barrier plug.

Figure 1: The RX-PC interface

Figure 2: Example embodiment

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The high-level process flow is:


1. Start with an Extremely Thin Silicon on Insulator (ETSOI) substrate


2. Form pad oxide and pad nitride


3. Pattern Rx on FET1


4. Etch STI trench around FET1


5. Deposit hi-k liner


6. Fill trench with High-Aspect-Ratio-Process (HARP) oxide


7. Block FET1 area and repeat sa...