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Named Abstraction for Layout Organization and Placement [DataStackImage] Disclosure Number: IPCOM000224103D
Publication Date: 2012-Dec-07
Document File: 2 page(s) / 36K

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The design of a very large scale integrated circuit (VLSI) is an inherently complex process where a logical description must be translated to a physical implementation . Frameworks are known that give each entity in a logical description a column in which to place the entity. One such framework is disclosed in US patent 7,082,595 and shows layout placement data at the schematic level. The framework disclosed in the patent presents a number of problems which are resolved by this invention.

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Named Abstraction for Layout Organization and Placement [DataStackImage]

The framework disclosed in US patent 7,082,595 works well for physical macros that are regular and unchanging in the placement location, but not when the placement of data elements are not regular. For example, in a data aligner, it is convenient to group all of the bits from different bytes together, so that a rotation from byte to byte uses short wires. In this type of structure, it would be preferred if bits 0,8,16, and 24 were placed in columns 0,1,2,3. However, using the framework of the patent, each bit would instead have to have a specified (unique) column location, which could easily introduce errors in the process.

As another example, a macro that has three physical columns for logic and latches associated with two logical bits is too complex to describe on a bit by bit basis. Some elements would have to be explicitly placed in columns 0,2,3,5,6,7 and other elements would be placed in columns 1,1,4,4, etc. Maintaining all of the elements of this translation would be cumbersome.

Experimenting with different floor plan arrangements using the framework of the patent would be time consuming. Changing the column assignments for various elements would involve going into the schematic at every level of hierarchy and making changes on every instance. This would discourage exploration of alternative physical implementations.

Disclosed is a method that annotates element placement information in order to overcome the limitations of the framework described in the patent.

Specifically, the method of the invention provides a name space that is created to describe the relative placement information. Use of the name space provides two primary advantages: 1) complicated intermixing of particular data bits is more easily accomplished, and 2) the placement of a macro can be reengineered in a single step with minimal designer intervention.

In a specific embodiment, the method of the invention generates a name space for columns, rows, and other floor planning elements of a layout at the schematic level. The name space is then used to facilitate the creation of the respective layout. A name space is created in such a way as to allow simple sharing across many different physical cells thereby permitting the name space to be shared across both hierarchy and from one macro to another. The name space is constructed in such a way so that advantage can be taken of grouped instances in a schematic and use the schematic grouping to help provide indexing into the name space.

The method of the invention involves two distinct characterizations. The first is a description of the name space which is called the dsImage, and the other provides a reference to the name space for particular instances which is called the dsType.

The dsIm...