Epitaxial Re-growth in the Source/Drain Region for Improved Performance of III-V FinFET/Trigate Devices
Publication Date: 2012-Dec-13
The IP.com Prior Art Database
A method of forming III-V FinFET/Trigate transistors that includes source/drain region etch out followed by epitaxial re-growth in the source/drain region and thereby improving performance of III-V FinFET/Trigate devices is disclosed.
Page 01 of 6
Epitaxial Re-growth in the Source/Drain Region for Improved Performance of III -V
Disclosed is a method for providing source/drain region etch out followed by epitaxial re-growth in the source/drain region for improved performance of III-V FinFET/Trigate devices. The high performance needs of III-V FinFET/Trigate kind of transistors have been integrated through a simple process flow as described below. The process flow also includes formation of self-aligned metal contacts on III-V FinFET/Trigate transistors.
Process Flow InGaAs stack and Reactive Ion Etching (RIE) fin definition as shown in Figure 1
The method disclosed then includes steps of Dielectric deposition followed by gate metal deposition, Chemical Mechanical Polishing (CMP) and nitride deposition as shown below in the Figure 2.
Page 02 of 6
Then the Dielectric is removed from outside gate regions as shown in Figure 3.
The next step in the process flow is the Spacer deposition as shown in Figure 4.
Page 03 of 6
RIE over etching of spacer as shown in Figure 5.
Wet etching of source/ Drain (S/D) regions as shown in Figure 6.
Page 04 of 6
Epitaxial re-growth of III-V in S/D regions as shown in Figure 7.
The next step is the Blanket metal deposition for self-aligned contacts as shown in
Page 05 of 6
The final step in the process flow is performing Chemical Mechanical Polishing
(CMP) as shown in...