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Epitaxial Re-growth in the Source/Drain Region for Improved Performance of III-V FinFET/Trigate Devices

IP.com Disclosure Number: IPCOM000224212D
Publication Date: 2012-Dec-13
Document File: 6 page(s) / 157K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method of forming III-V FinFET/Trigate transistors that includes source/drain region etch out followed by epitaxial re-growth in the source/drain region and thereby improving performance of III-V FinFET/Trigate devices is disclosed.

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Epitaxial Re-growth in the Source/Drain Region for Improved Performance of III -V

FinFET/Trigate Devices

Disclosed is a method for providing source/drain region etch out followed by epitaxial re-growth in the source/drain region for improved performance of III-V FinFET/Trigate devices. The high performance needs of III-V FinFET/Trigate kind of transistors have been integrated through a simple process flow as described below. The process flow also includes formation of self-aligned metal contacts on III-V FinFET/Trigate transistors.

Process Flow InGaAs stack and Reactive Ion Etching (RIE) fin definition as shown in Figure 1

Figure 1

The method disclosed then includes steps of Dielectric deposition followed by gate metal deposition, Chemical Mechanical Polishing (CMP) and nitride deposition as shown below in the Figure 2.

1


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Figure 2

Then the Dielectric is removed from outside gate regions as shown in Figure 3.

Figure 3

The next step in the process flow is the Spacer deposition as shown in Figure 4.

2


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Figure 4

RIE over etching of spacer as shown in Figure 5.

Figure 5

Wet etching of source/ Drain (S/D) regions as shown in Figure 6.

3


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Figure 6

Epitaxial re-growth of III-V in S/D regions as shown in Figure 7.

Figure 7

The next step is the Blanket metal deposition for self-aligned contacts as shown in

Figure 8.

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Figure 8

The final step in the process flow is performing Chemical Mechanical Polishing
(CMP) as shown in...