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Scan Structure for the Clock Generation Module

IP.com Disclosure Number: IPCOM000225262D
Publication Date: 2013-Feb-04
Document File: 7 page(s) / 648K

Publishing Venue

The IP.com Prior Art Database

Abstract

In this paper, we propose a DFT (Design For Test) structure to improve clock generation module test coverage greatly without complicating CTS (Clock Tree Synthesis). The proposed DFT structure includes a scan chain connection scheme in which the clock generation module flip-flops can be put into the scan chain during DC scan mode and excluded from the scan chain during AC scan mode. The proposed DFT structure also includes clock gating control logic to eliminate cross clock domain violations so there is no need to balance the clock tree of the clock generation module with other system clocks.

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Scan Structure for the Clock Generation Module

Abstract:

In this paper, we propose a DFT (Design For Test) structure to improve clock generation module test coverage greatly without complicating CTS (Clock Tree Synthesis).  The proposed DFT structure includes a scan chain connection scheme in which the clock generation module flip-flops can be put into the scan chain during DC scan mode and excluded from the scan chain during AC scan mode.  The proposed DFT structure also includes clock gating control logic to eliminate cross clock domain violations so there is no need to balance the clock tree of the clock generation module with other system clocks. 

1.   Introduction

For a SOC, the clock generation module is normally a major lost test coverage contributor because most flip-flops in the clock generation module cannot be put into the scan chain for the following reasons:  1) Clock dividers/controllers are needed to generate internal at-speed test clocks from PLL for AC scan; and 2) the clock source for clock dividers/controllers is asynchronous to other system clocks, it would complicate CTS or scan chain insertion if we want to put clock divider flip-flops into scan chain using traditional method.  As a result, the overall test quality may not meet requirement, or we need to add many functional test patterns to cover it which is not test time and test cost efficient.

In this paper we introduce a scan structure for the clock generation module so that its test coverage could be improved significantly, without complicating existing CTS and scan insertion flow. The detailed implementation circuit will be introduced in the following sections.

2.   Detailed Implementation

Figure 1: Overview of the Embodiment

An overview of the embodiment is shown in Figure 1, which includes two mainly control circuits. The control circuit to include the flip-flops of the clock generation module into scan chain has been illustrated in 101. And the clock gating control logic to eliminate the cross clock domain violation has been showed in 102.

2.1 Embodiment to bypass the scan chain

The detailed implementation of circuit 101 illustrated in Figure 1 is shown in Figure 2.  As shown in Figure 2, a scan chain bypass MUX 201 controlled by DC scan mode signal is added to include the clock generation module flip-flops into scan chain during DC scan mode and excluded them from the scan chain in AC scan mode.

An AND 202 is added to generate the scan enable for the clock generation module. Obviously, the scan enable is gated by the DC scan mode signal so that the clock generation module is put in scan mode during any scan mode when internal clock is not necessarily needed, while during AC scan mode the clock generation module is put in functional mode and it could generate internal clocks for at-speed test.

A MUX 203 is added to select the clock source of the clock generation module. The function is simple, scan_clk is transferred to the clock generation module in DC scan m...