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Browse Prior Art Database

Fault Testable Signal Divider

IP.com Disclosure Number: IPCOM000225372D
Publication Date: 2013-Feb-12
Document File: 2 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a testable divider that identifies when the test mode is enabled, and then breaks the feedback loop and injects the desired test signal through the dividing logic. When test mode is not enabled, the feedback loops function normally by storing signal states.

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Fault Testable Signal Divider

The pass-through divider was created to pair with a stuck-at fault testable performance screen ring oscillator (PSRO) macro. The PSRO macro has a test enable function that is used to validate defect free logic function by manually flipping the state of all logic. When the test enable function is not in use the PSRO generates an oscillating signal. The macro needs a divider to reduce the output signal to a measurable frequency while retaining the stuck-at fault test function of the PSRO. A standard signal divider works during normal operation, dividing the signal by factors of two. However, standard signal dividers use feedback loops to identify, store, and delay signal switching. If a non-oscillating signal is fed into a feedback loop divider the output can be inconsistent due to previous states stored in the feedback loop.

The design is a divider that allows the input signal to pass through when test mode is enabled. When in test mode the logic breaks the feedback loops and forces the desired test signal through the dividing logic. When test mode is disabled the feedback loops function normally by storing signal states.

The divider has three inputs: CLK, CLKN, and TE. CLK is the signal to be divided and CLKN is the inverted signal of CLK. TE is the test enable input. NOR gates are placed into the feedback loops with one input connected to TE and one to the inverted feedback loop signal. When TE is low (0), the feedback signal is pa...