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INNOVATIVE CYCLE ACCURATE TESTING METHODOLOGY FOR FUSE BLOWN SILICON

IP.com Disclosure Number: IPCOM000225982D
Publication Date: 2013-Mar-19
Document File: 5 page(s) / 470K

Publishing Venue

The IP.com Prior Art Database

Abstract

Modern day SoCs (System on Chip) contain a fuse box to burn memory repair information and enable/disable SoC features. During the lifetime of SoC, the fuse box needs to be read each time a device reset is performed. The fuse box read time is proportional to the amount of information burnt in the fuses. As fuse information will vary from silicon to silicon, fuse read time varies from silicon to silicon. This paper discusses various issues involved with testing devices containing a fuse box and defines a new methodology for tester pattern generation, pattern conversion and running on tester such that patterns remain cycle-accurate and stable for both virgin and fuse blown dies.

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Innovative Cycle Accurate Testing Methodology for Fuse Blown Silicon

ABSTRACT

Modern day SoCs (System on Chip) contain a fuse box to burn memory repair information and enable/disable SoC features. During the lifetime of SoC, the fuse box needs to be read each time a device reset is performed.  The fuse box read time is proportional to the amount of information burnt in the fuses.  As fuse information will vary from silicon to silicon, fuse read time varies from silicon to silicon.  This paper discusses various issues involved with testing devices containing a fuse box and defines a new methodology for tester pattern generation, pattern conversion and running on tester such that patterns remain cycle-accurate and stable for both virgin and fuse blown dies.

BACKGROUND

Modern day SoCs contain many on-chip memories that are prone to manufacturing faults. Faulty memories result in non-functional silicon, hence lower yields. To handle this problem, redundancy is added to memories to allow usage of spare and redundant memory locations in place of faulty words.

Memory Build-In-Self-Test (MBIST) and Build-In-Self-Repair (BISR) techniques are used to test the memories for various manufacturing faults and replace faulty words with spare words. The required memory repair information is maintained by burning fuses inside an on-chip fuse box. During normal operation, the fuse box contents are read on startup to configure replacement spare words for faulty memory words.

In addition to memory repair, the fuse box is also used to maintain fuses to control functionality and features of a particular SoC like disabling set of cores of multi-core SoC or enabling/disabling some features like encryption engine, serdes, DDR controller, etc.  Fuses are burnt and programmed during testing to create different personalities of the same SoC.

A fuse box supports only a limited number of reads.  During functional usage of SoC on device boards, the fuse box needs to be read each time the device is reset.  The fuse box read time is proportional to the amount of information burnt in the fuses. As amount of memory repair information will vary from silicon to silicon, fuse read time varies from silicon to silicon.

ISSUE DESCRIPTION

During SoC testing on ATE, a large number of patterns is executed such as for different voltage and temperature conditions.  Pattern categories include AC scan, DC Scan, Memory BIST, Max Frequency (FMAX), Power testing, Core functional, SoC functional, Interface AC spec characterization, etc.

Total Pattern count can vary from a few hundred to 1000+ for different SoCs. Each pattern is tested multiple times on the same silicon at 3 voltages X 2 Temperatures at Wafer Probe and on packaged silicon. Hence, assuming 1000 patterns, the silicon is taken through the reset sequence 12,000 times (1000 X 3 X 2 X 2) before the device even reaches the customer.

So, ATE (Automated Test Equipment) testing of silicon is impacted by 3 significant issues:

1.    Unn...