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Reduced-SER Bulk FinFET Latches on High-Speed CMOS

IP.com Disclosure Number: IPCOM000226243D
Publication Date: 2013-Mar-25
Document File: 2 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

Improved SER immunity FINFET by thinning the isolation region under the gate and doping the bottom of the FINFET for isolation.

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Reduced-SER Bulk FinFET Latches on High-Speed CMOS

A FINFET with improved Soft Error Failure rates is constructed by thinning the Isolation region under the gate and doping the bottom of the FINFET for isolation.

On the left-hand side of the figure below, a standard bulk -based FinFET is illustrated. The isolation oxide serves to electrically isolate the gate electrode from the substrate. A so-called 'sub-fin' region of the fin extends below the gate electrode, and is surrounded by the isolation oxide. This sub-fin must be highly doped to prevent punch-through current from leaking between source and drain (not shown, out of plane), since the gate electrode does not gate this region. When exposed to ionizing radiation, this isolation oxide can trap (usually positive) charge which eventually can invert the sub-fin to a conductor, causing the off-state current of the FinFET to be too large, and causing circuits to fail.

On the right-hand side of the figure below, the isolation oxide has been made very thin, (e.g. comparable to that of the gate dielectric thickness). This greatly reduces sensitivity to the creation of off-state inversion since a lower amount of total charge is trapped for a given radiation does, and additionally the gate electrode significantly reduces the electrostatic effect any trapped charge will have on the sub-fin potential.

This design thus provides enhanced immunity to radiation dose exposure for FinFET circuits.

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