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Reliability Screen Timing Method Disclosure Number: IPCOM000226252D
Publication Date: 2013-Mar-25
Document File: 2 page(s) / 40K

Publishing Venue

The Prior Art Database


Disclosed is a timing methodolgy for a reliability screen test plan that varies voltage based upon process.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 01 of 2

Reliability Screen Timing Method

Reliability Screens (e.g., Burn In, Dynamic Voltage Screen) require closing timing at use conditions (voltage) higher than client use conditions. In newer technologies, timing closure at higher voltages is becoming more difficult. This results in long turnaround time (TAT) to complete design. In addition, the use of higher performance/higher power library elements results in higher power at client use conditions. Many products now use Selective Voltage Binning (SVB) to process a window bin set. Faster (higher power) parts will run reliability screens at lower voltages. If Reliability Screen conditions can be planned when a product is timed, then the product can be timed at a lower voltage, have lower power, and require a shorter Design TAT.

Figure 1: Enabling Patent Background (Figure references Dynamic Voltage Screen (DVS), Enhanced Voltage Screen (EVS))

Figure 2: Standard SVB (16 bins)


Page 02 of 2

The solution is a timing method that supports a reliability test plan for products that vary voltage at system level based upon process. The n-bin SVB flow model is used. Novel contributions of the invention include methods to:

• Identify client use conditions (SVB)

• Identify Reliability Screen Conditions (X factor based on use condition rather than technology max or product max) for each SVB Bin

• Identify "timing bins"; limited set of timing runs that cover use

• Perform Timing Runs at designated conditions

• Perform R...