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Fin level local interconnect for SOI finfets

IP.com Disclosure Number: IPCOM000226319D
Publication Date: 2013-Mar-27
Document File: 2 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to lower PC to CA capacitance by use of buried local interconnects.

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Fin level local interconnect for SOI finfets

Capacitance is a limiting factor for performance improvement for future nodes especially so for FinFET technology.

Disclosed is a method to lower PC (gate) to CA (source-drain contact) capacitance by use of buried local interconnects. The invention incorporates the following:


 Structure: Fin level LI used to merge fins and provide local routing


 Intentional oxide gouging may be done to increase the height of the LI


 This greatly relaxes CA design requirements. Now CA can be via like if needed.

There are two embodiments for this invention:

1. Without Shallow Trench Isolation (STI): For which the buried LI is not self- aligned. However for this embodiment, the buried LI (local interconnect) can be used to wire up two transistors (Figures 1 and 2)

2. With Shallow Trench Isolation: In this case, the LI may be self-aligned to RX (Device region) if desired.

Figure 1: Flow Step 1

Figure 2: Flow Step 2

1


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The gate nitride HM (hard mask) is used here (similar to gate first Self-Aligned Contact (SAC)); therefore, no additional step for SAC protection is needed. In addition, because the process is etching metal selectively to ILD, better selectivity may be obtained.

Figure 3: Additional views

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