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Automated ECO Flow for overall cycle time reduction

IP.com Disclosure Number: IPCOM000226463D
Publication Date: 2013-Apr-04
Document File: 4 page(s) / 346K

Publishing Venue

The IP.com Prior Art Database

Abstract

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity. The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turn around time. With the increasing logic size and complexity in SOC’s as well as development of complex techniques of logic optimization during synthesis, compounded with the absence of any stable ECO flow/ tool it is becoming difficult to implement ECOs in the design.

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Automated ECO Flow for overall cycle time reduction

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity.

The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turn around time.

With the increasing logic size and complexity in SOC’s as well as development of complex techniques of logic optimization during synthesis, compounded with the absence of any stable ECO flow/ tool it is becoming difficult to implement ECOs in the design.   

Although there are tools in the market that support ECO implementation but they are mostly unstable and inconsistent. The major issues seen in the existing tools are:

•        Huge runtime: The existing tool flow requires full SOC synthesis which could consume 2-3 days depending on the design size.

•        Large Patch size:  Generally the patch generated by these tools is larger than required.

•       Setup Time: The setup generation time for ECO tool also becomes a limitation for using it in most of the cases.

Flow used by existing tools in the industry:

FLOW CHART 1

As can be seen from the Flow-chart 1, this process requires a full chip synthesis corresponding to the new RTL.  The approach also does not account for boundary optimization that occurs during synthesis, the patch that is generated is usually larger than required. The main disadvantages of this flow are therefore the huge runtime that is required for the synthesis of the new RTL as well as for setup generation. Even after spending all this time on ECO implementation it is not ensured that the resulting ECOed netlist will be LEC clean.

If the existing flow fails then the synthesis engineer is left with the only option of manually implementing the ECOs. Now this has its own challenges. It is difficult and very time consuming to implement a large number of ECOs manually. Also the need to implement a single ECO on multiple DBs involves a lot of man hours and efforts. This once again calls for the need of a new and faster way of ECO implementation with less manual intervention.

All the above mentioned factors lead to the development of the idea discussed in this paper.

The idea provides a fast and automated way to implement complex ECOs. The turn-around time of the flow is less, so ECOS that we encounter very late in Design cycle can also be accommodated.

·         The proposed flow will signific...