Browse Prior Art Database

A Method and System for Controlling Semiconductor Design Attributes

IP.com Disclosure Number: IPCOM000227747D
Publication Date: 2013-May-14
Document File: 3 page(s) / 50K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for controlling design attributes and preventing redesign of semiconductor designs is disclosed. The method and system identifies an allowed variation for each key attribute of a semiconductor design and if the variation exceeds an allowed limit then project viability is re-quoted / assessed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 83% of the total text.

Page 01 of 3

A Method and System for Controlling Semiconductor Design Attributes

There are various teams involved in execution of a semiconductor design. For example, a package team designs the package, a physical design team performs timing and layout, a noise team determines level of decoupling capacitors, and a power team estimates power. The changes made by one team can impact other teams. Many a times the changes by one team are not known until the end of the design resulting in redesigning of the semiconductor designs. Specifically, power changes can require complete package and noise redo.

Disclosed is a method and system for controlling design attributes. The method and system identifies key attributes such as, but not limited to, power. The allowed variation for the identified key attribute is calculated. The method and system establishes a baseline for a product, quote or other design point based on a composite attribute. The method and system evaluates netlist content at one or more points such as, but not limited to, at start of design, when a change is submitted by a client and at key design checkpoints. Thereafter, the method and system identifies when the composite variation exceeds the allowed limit. Upon identifying that the composite variation exceeds the allowed limit, the method and system re-quotes and assesses project viability.

Fig. 1 illustrates a data flow diagram explaining package/design power interlock in accordance with an embodiment of the metho...