Browse Prior Art Database

A Novel Approach to Detect X Propagation Non Resettable Flops for Faster Gate Level Simulation Initialization

IP.com Disclosure Number: IPCOM000228104D
Publication Date: 2013-Jun-06
Document File: 5 page(s) / 363K

Publishing Venue

The IP.com Prior Art Database

Abstract

One of the key challenges in gate level simulation of an ASIC/SoC is X (unknown) propagation debug. X propagation occurs due to uninitialized memory, timing violations and non-resettable flops. X propagation due to non resettable flops are very difficult to debug and consume enormous time; the presence of hundreds/thousands of such non resettable flops aggravates the chances of X propagation. To avoid these X, such non resettable flops are required to be initialized with a random value 0 or 1 in the beginning (at 0 time) using system tasks such as $deposit to mimic silicon behavior but the problem is tha the list of such pure non resettable flops is not known to the SOC team. Thus, with every X propagation, such non resettable flops are identified one by one in GLS simulation, which consumes significant GLS time, which greatly impacts the gate level schedule. In this paper we propose a methodology that can generate a list of non resettable flops required to avoid ‘X’ propagation in gate simulation. This approach uses formal tools and gate level VCD of the physical design to generate the list of such flops.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 36% of the total text.

TITLE 

A Novel Approach to Detect X Propagation Non Resettable Flops for Faster Gate Level Simulation Initialization

ABSTRACT

One of the key challenges in gate level simulation of an ASIC/SoC is X (unknown) propagation debug. X propagation occurs due to uninitialized memory, timing violations and non-resettable flops. X propagation due to non resettable flops are very difficult to debug and consume enormous time; the presence of hundreds/thousands of such non resettable flops aggravates the chances of X propagation. To avoid these X, such non resettable flops are required to be initialized with a random value 0 or 1 in the beginning (at 0 time) using system tasks such as $deposit to mimic silicon behavior but the problem is tha the list of such pure non resettable flops is not known to the SOC team.  Thus, with every X propagation, such non resettable flops are identified one by one in GLS simulation, which consumes significant GLS time, which greatly impacts the gate level schedule.  In this paper we propose a methodology that can generate a list of non resettable flops required to avoid ‘X’ propagation in gate simulation. This approach uses formal tools and gate level VCD of the physical design to generate the list of such flops.

INTRODUCTION

Gate level simulations are almost mandatory these days for every complex SoC (System on Chip). As design complexity increases, gate level verification becomes very challenging and time consuming task. Basic question arises in minds of many “why do we need gate level simulation when STA (static timing analysis) and formal verification is done”. There are multiple reasons for this.

§  STA (Static Timing Analysis) may set false and multi cycle paths where they don’t belong – wrong understanding of the design may lead to wrong false path definition.

§  Validate asynchronous flop to flop paths which STA doesn’t cover.

§  DFT verification. Since scan-chains are inserted after RTL synthesis.

§  BCS/WCS Timing simulation with back annotated SDF to validate dynamic switching.

§  ATE (Automatic Test Equipment) tester pattern generation from SDF (Standard Delay Format).

§  For switching factor to estimate power

§  Identify any faulty initial condition of the flop – X/Z, RTL simulation is normally optimistic.


What is X : On silicon, X has no existence. Basically, it is some uncertain value but, to mimic this uncertain behavior, which is sometimes achieved from meta-stability, hardware description language like Verilog provides an attribute termed X. For synthesis, it is don’t care i.e. '0' or '1', whatever reduces the number of gates required to implement an RTL logic but for simulations, it is some unknown value. To understand it well, let’s analyze its behavior in analog and digital domain separately. In digital domain X can be either a 0 or 1. It’s unpredictable. In analog domain, there is no any such term. However, we can say X is any unpredictable voltage level between ground and VDD v...