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8 bit/10 bit Early Late Phase Detector

IP.com Disclosure Number: IPCOM000228190D
Publication Date: 2013-Jun-12
Document File: 4 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Programmable 8-bit or 10-bit Early Late Phase Detector

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This is the abbreviated version, containing approximately 55% of the total text.

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8 bit/10 bit Early Late Phase Detector

The invention provides a single circuit for 8 bit & 10 bit mode early late phase detector at 15Gbps at a very low voltage of 0.7V. The previous known solution provides for only 8 bit mode early late detection at 8Gbps at 0.85V supply.

This unique solution can be used in applications where both 8 bit and 10 bit mode are used at a very low voltage of 0.7V.

Abstract


A phase detector which provides to the CDR logic a measurement of the incoming data signal phase relative to the internally generated recovered clock. The architecture has been modified to work for both 8bit and 10bit modes at upto 16Gbps. On each C16 or C20 cycle, it provides a 2 bit result to the RX RLM which indicates whether the majority of the data transitions during the previous 16UI or 20UI span were "early" or "late" relative to the recovered clock transitions. The CDR algorithm implemented in the RX RLM uses the early and late information to adjust the phase of the recovered clock to match that of the incoming data stream.

Figure 1. shows the block diagram of the claim.

Description of the Claim:

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Figure 2. shows the extended block diagram of the claim.

The early late Phase detector gets four data and four edge input samples from a 2:4 deserializer. The phase detector determines the early/late result by comparing data samples of the received signal taken by both the edge and data sampling paths. The edge path samples are timed with both transitions of the recovered clock. The data samples are taken at a defined phase offset (nominally 90 degrees) from the recovered clock. The goal of the CDR control loop is to tune the phase of the recovered clock so that the edge samples are taken at the transitions in the input signal. Once this alignment is achieved, the data samples are centered in the signal eye and have the lowest possible error rate.

For each UI, the detector compares the edge sample to the current and previous data samples to arrive at one of the three possible results: Early, Late or 0. The Early and Late timing relationships are illustrated in Figure 3.

Table 1. shows the truth table for early lat...