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Adaptive RET verification recipe in a dynamic lithographic and EDA environment

IP.com Disclosure Number: IPCOM000228196D
Publication Date: 2013-Jun-12
Document File: 9 page(s) / 159K

Publishing Venue

The IP.com Prior Art Database

Abstract

To run additional flow after the existing verification flow and prior to manual inspection. New flow should get rid of all false, redundant, & waiver counterparts errors. Flow should run ONLY at error locations. Should not be time consuming. The new flow has to be adaptive. Verification method will depend on the type of process models used. It will also depend on the layer & keyword being verified. New flow is generated automatically to save the time needed for development. All the new features can be placed in the core of the new flow and specific flows for each keyword is generated automatically.

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Page 01 of 9

Adaptive RET verification recipe in a dynamic lithographic and EDA environment


Introduction

- RET verification

    - Dynamic EDA & lithographic environment.
Problem description


- False errors


- Redundant errors

    - Waivers Prior art
New flow


- Main feature


- Part I eliminates false/redundant errors


- Part II eliminates waivers counterparts

    - Combined flow
Benefits

RET Verification

Dynamic environments


Dynamic EDA environment

- Introducing new verification packages, i.e. more accurate dense solution method.


- Introducing new features/functionalities.

- It is NOT reasonable to update our verification flows every time a new solution/feature is released


- New features may have a run time penalty.


Dynamic lithographic environment

- Engineer may slightly modify the process which cause a shift in our models.


- Process may shift!

- Some errors shapes are known priory to be safe on silicon that are hard to code in the verification recipe.

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Page 02 of 9

Problem Description

False errors
Old verification recipes are flagging a huge number of false errors.

- This is because, they have many user-input settings.


- Users always compromised run time versus accuracy.


- Users ensured that real errors are not missed.


Time needed to inspect them increases.


Process of fixing the OPC recipe becomes iterative


TAT (turn-around time) is blown up.

Redundant errors


Similar errors are flagged at several locations.

- Physically they are the same error and need the same OPC fix.


This increases the inspection run time and TAT as well.

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Page 03 of 9

Waivers


Verification recipes rule checks may comprise many waivers that are known priory to be safe on silicon.


A waiver is defined as a certain combination of shapes plus an error property associated with it.


Waivers counterparts need to be eliminated, so the engineer will focus on real issues.

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Page 04 of 9

Prior art US756233

Solution Main feature


To run additional flow after the existing ve...