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Test Time and Peak Power Reduction During At-Speed Testing of Identical Cores

IP.com Disclosure Number: IPCOM000228920D
Publication Date: 2013-Jul-12
Document File: 6 page(s) / 298K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method to prevent over current spikes during at-speed testing generates staggered pulses for a capture clock in the same capture cycle as at-speed testing. The staggered clock pulses are programmable and allow users to select any combination of cores to be tested in AC scan. This approach solves the problem of peak power issues and at the same time allows testing of multiple identical cores for both broad side and launch-on-shift approaches. The test time reduction is achieved as the paths for the multiple cores can be tested in the same capture cycle. It also allows testing of combinational logic present between different identical cores working on the same or synchronous clock of the core clock.

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Test Time and Peak Power Reduction During At-Speed Testing of Identical Cores

Abstract

A method to prevent over current spikes during at-speed testing generates staggered pulses for a capture clock in the same capture cycle as at-speed testing.  The staggered clock pulses are programmable and allow users to select any combination of cores to be tested in AC scan.  This approach solves the problem of peak power issues and at the same time allows testing of multiple identical cores for both broad side and launch-on-shift approaches.  The test time reduction is achieved as the paths for the multiple cores can be tested in the same capture cycle.  It also allows testing of combinational logic present between different identical cores working on the same or synchronous clock of the core clock.

Introduction

In a typical SOC, the functional clock pulses in the capture cycle of at-speed testing are generated by a divided PLL clock or a reference clock fed to the chopper circuit (special digital block), which generates the clock gating cell enable.  The launch and capture pulses are generated based on the pattern loaded to the chopper’s internal register during shift cycle of at-speed testing.  This shift register is shifted out in capture cycle on the functional clock frequency and generates the clock gating cell enable.

In a multi-core system, most of the cores operate on the same clock source usually at a frequency of the order of 500 MHz to 1 GHz.  The size of these cores is increasing to accommodate complex design features.  These multiple cores operating on a single clock source will receive the capture clock edges at the same time during at-speed testing.  This simultaneous toggling of clock pulses may create a peak power issue during the capture cycle of at-speed testing.  The peak power issue becomes more significant with the increase in clock frequency.  If most of the cores are on the same power rail, the peak power issue can create reliability issues.

This simultaneous toggling of capture clock pulses can be avoided by enabling the cores one by one and testing the individual, identical cores with separate at-speed test patterns.  This technique can solve the above-discussed peak power issue, but it increases pattern count, which impacts test time.  This method does not allow inter-domain testing of paths between the cores.

In this paper we propose a method that solves the above-listed problems by generating the staggered pulses of the capture clock in same capture cycle of at-speed testing.  These staggered clock pulses are programmable and allow users to select any combination of cores to be tested in AC scan.  This approach solves the problem of peak power issues and at the same time allows testing of multiple identical cores for both broad side and launch-on-shift approaches.  The test time reduction is achieved as the paths for the multiple cores can be tested in the same capture cycle. It also allows testing of combi...