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METHOD TO REDUCE SUPPLY DROOP IN POWER GATED IMPLEMENTATIONS

IP.com Disclosure Number: IPCOM000228930D
Publication Date: 2013-Jul-15
Document File: 6 page(s) / 899K

Publishing Venue

The IP.com Prior Art Database

Abstract

Power gated implementations are challenging. First and foremost, such designs require two power grids (always ON grid and power gated grid) which have to share metal resources. In such cases, using a conventional power grid design approach causes higher voltage droop. This results in either a yield loss or stringent design boundaries (e.g., additional timing margins) or both. To mitigate this voltage droop, larger power switches are required (which have lower effective resistance). However, this approach increases the overall power and area. The method described below helps cope with the higher voltage droop challenge by using an always ON grid only over the power switches and customization of power grid metals at strategically selected locations.

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METHOD TO REDUCE SUPPLY DROOP IN POWER GATED IMPLEMENTATIONS

Introduction

Power gated implementations are challenging. First and foremost, such designs require two power grids (always ON grid and power gated grid) which have to share metal resources. In such cases, using a conventional power grid design approach causes higher voltage droop. This results in either a yield loss or stringent design boundaries (e.g., additional timing margins) or both.  To mitigate this voltage droop, larger power switches are required (which have lower effective resistance).  However, this approach increases the overall power and area.  The method described below helps cope with the higher voltage droop challenge by using an always ON grid only over the power switches and customization of power grid metals at strategically selected locations.

Body

There is a voltage droop limit for any SoC to ensure its functionality.  The effective voltage at a transistor should be greater than the worst voltage at which the timing is closed.  In this paper we provide a process to ensure that, in power gated designs, voltage droop is minimized (or at least within specified limits) so that maximum speed of operation on Silicon can be achieved.  Compared to design without power switches, the always ON/gated grids are sparse in power gated implementations.  It is desirable to reduce voltage droop without any area and/or routing resource penalty.

            Figure 1 depicts a typical block of a SoC.  The hard sub-modules (such as memories) are marked.  The vertical white lines are the always ON grid M7.  The power switches are placed in columns at a constant pitch in the SOG portion of the design.  In case of hard sub-modules, there are no power switches inside as their non-power gated versions are used.  Instead, power switches are placed at the edges of these hard sub-modules, as shown in figure 2.

FIGURE 1

FIGURE 2

Customized always ON power grid over power gates

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