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A Method and System for Deep Trench Leakage Protection

IP.com Disclosure Number: IPCOM000229264D
Publication Date: 2013-Jul-17
Document File: 5 page(s) / 104K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for Deep Trench (DT) leakage protection is disclosed. The method and system uses localized oxidation for improved isolation. An additional box for leakage is created during the process.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 79% of the total text.

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A Method and System for Deep Trench Leakage Protection

Leakage to substrate in Deep Trench (DT) capacitors is a proverbial problem. Recess steps are hard to control and as geometries shrink, it becomes even more of a problem. The result can be a leakage path to substrate through the DT. The large density of DT capacitors used makes this a particularly large problem when current densities reach a high level.

Disclosed is a method and system for Deep Trench (DT) leakage protection. The method and system uses an oxide growth to create improved isolation for DT at the Buried Oxide (BOX) bulk silicon area. This is left during the rest of the processing to provide an additional block for leakage. The method starts with a standard process as shown in fig. 1.

Figure 1

Thereafter, a DT mask is opened into the substrate as shown in fig. 2.

Figure 2

1


Page 02 of 5

Subsequently, the oxidation step is performed as shown in fig. 3.

Figure 3

Thereafter, the Reactive-Ion Etching (RIE) process is competed till the depth of the capacitor as shown in fig.4.

Figure 4

Subsequently, a dielectric and conductive layer is deposited as shown in fig.5.

2


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Figure 5

After deposition of the dielectric and conductive layer, doped polysilicon is filled as

shown in fig.6.

Figure 6

The doped polysilicon is thereafter recessed as shown in fig.7.

3


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Figure 7

After recessing the doped polysilicion, the masking is removed as shown in fig. 8 and a standard gate process is init...