Browse Prior Art Database

Structure for inter-reticle alignment in semiconductor manufacturing

IP.com Disclosure Number: IPCOM000230109D
Publication Date: 2013-Aug-20
Document File: 1 page(s) / 19K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a wiring-level structure between 'n' reticle fields to determine cross-wafer alignment and inter-reticle alignment. This structure reduces the time needed to measure alignment across parts of a wafer.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 1

Structure for inter-reticle alignment in semiconductor manufacturing

When parts of the wafer are misaligned, there is a risk for severe yield loss.

It is difficult to determine the extent of misalignment without numerous time-consuming inspections. Large chips that span multiple reticle fields are especially at risk.

Currently, alignment is measured by optically scanning reticle fields and measuring alignment marks. Sampling every field is very time-intensive.

To address this, the invention is a wiring-level structure between 'n' reticle fields to determine cross-wafer alignment and inter-reticle alignment. The structure spans the wafer across multiple reticle fields. This structure is electrically tested to determine inter-reticle alignment across the wafer and is sensitive to both x- and y-direction misalignment. The device can be constructed at any wiring level.

If the test fails, then it indicates that there is a misalignment problem on the wafer. Testing at M1 level also indicates a misalignment problem with the Front End of Line (FEOL) devices.

The structure is similar to a step function that crosses reticle fields. Contact pads at various locations along the structure to measure inter-reticle alignment.

Figure: Structure (in red) placed in dicing channel, spanning multiple reticle fields

1