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User Space TCE Bypass for RDMA

IP.com Disclosure Number: IPCOM000230708D
Publication Date: 2013-Sep-04
Document File: 2 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention describes a method to bypass an adapters MMU unit for virtual to physical addressing from userspace. Said inventions details a mechanism whereby the kernelspace driver and userspace library perform an exchange to acquire the physical addressing data backing a virtual address, as well as a SW indexing mechanism to preserve the virtual addressing APIs presented to userspace applications.

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User Space TCE Bypass for RDMA

A modern trend in systems IO is kernel bypass technologies. One clear example of this is RDMA, where traditional kernel multiplexed protocols are executed in userspace with direct HW access for low overhead, high performance IO (Fig. 1). One of the main goals of exploiters are low latency data transfers.

Kernel bypass is achieved by registering user memory with the adapter, along with a method of ringing a doorbell on the adapter to signify work to do. The application makes use of a standardized API (libibverbs) to post the buffers to the adapter in a format the adapter recognizes. The adapter then DMA's the data directly to and from the user's memory.

To register memory, the user passes in the virtual address and length describing the memory block along with flags describing how it will be used. Because of the large amount of memory registrations desired, the tables describing memory registrations are usually kept in system memory with the adapter DMA'ing the table entries as it needs to. Memory registrations are involve keeping a record of the registration (permissions, virtual address, length, Keys (used by the adapter to identify which registration is involved). Memory registrations also involve keeping a list of bus addresses for every virtual address page (see Fig.


2).

When the application conducts a Post Send or Post Recv buffer, the adapter is forced to do at least two separate DMA operations per scatter/gather location. The first to get the memory registration entry and the...