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A Method to Decrease the Electrical Size of On-chip Decoupling Capacitor While Maintaining the Dynamic IR Drop

IP.com Disclosure Number: IPCOM000230884D
Publication Date: 2013-Sep-17
Document File: 4 page(s) / 442K

Publishing Venue

The IP.com Prior Art Database

Abstract

When an SOC wakes up from a sleep or semi-powered down state, there are high transients and thus a large demand for current. To mitigate this problem either wake up time is increased or more decoupling capacitors (decaps) are put in the SOC. Both of these solutions are inefficient with respect to SOC performance. A high number of decaps cannot be put in the SOC because of die area constraints as well as wake up time should be minimized, so there is a trade-off between wake up time and number of decaps used. We propose an approach that reduces the requirement of decaps by 50% for the same wake up time as in the conventional approach, or reduces the wake up time for the same number of decaps

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A Method to Decrease the Electrical Size of On-chip Decoupling Capacitor While Maintaining the Dynamic IR Drop

1.                              Abstract

When an SOC wakes up from a sleep or semi-powered down state, there are high transients and thus a large demand for current.  To mitigate this problem either wake up time is increased or more decoupling capacitors (decaps) are put in the SOC.  Both of these solutions are inefficient with respect to SOC performance.  A high number of decaps cannot be put in the SOC because of die area constraints as well as wake up time should be minimized, so there is a trade-off between wake up time and number of decaps used.  We propose an approach that reduces the requirement of decaps by 50% for the same wake up time as in the conventional approach, or reduces the wake up time for the same number of decaps.

2.                              Problem Definition

Current (mA) requirement from an on-chip decoupling capacitor during transients is much higher than during steady state operation.  To overcome the need for huge decoupling capacitors, we need to increase the wake up time, which impacts performance so there is a need for a solution that can reduce the number of decaps or minimize the wake up time.

3.                              Conventional Approach

General design practices today, which try to minimize the decap requirement at the time of wake up, are listed below,

·         Slow wake up/mode change time.

·         The granularity of frequency steps through the wake-up or mode change operations, for specified droops.

Both of these conventional approaches require more time to wake up the chip or more decoupling capacitors to reduce the wake up time

4.       Proposed Approach

The proposed Innovation is to not let the PDN see a transient demand of current, thereby eliminating the need for huge decoupling capacitors.

This is done by injecting the maximum average current into the PDN network during the steady state itself so that during the transient (wake-up or mode change), there is no sharp increase in the current since the average current required during the transient is already built into the PDN network.

This is implemented by inserting a slow programmable current sinking circuit in the PDN network. This circuit is switched on before any operation occurs in the device. The ESD clamps available in the I/O pads can be used for this purpose so that no extra area overhead is required to build this additional current sinking circuit into the device.  As a result, the amount of decoupling...