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Bipolar devices using SiC and SiGe

IP.com Disclosure Number: IPCOM000231098D
Publication Date: 2013-Sep-26
Document File: 5 page(s) / 53K

Publishing Venue

The IP.com Prior Art Database

Abstract

• Technology adder with potentially no change (embodiment I, free HBT) or minimal changes in process flow (embodiment II). Device takes advantage of BI contact (n+ epi region) to open area for NPN device growth. The base of said device is composed of the SiGe-B material of the standard SOI device source/drain regions. The emitter region of device is composed of the n+ insitu doped SiC material of the standard SOI device source/drain regions. A proposed embodiment following uses a standard contact scheme of offset contacts for each of the device regions.

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Bipolar devices using SiC and SiGe

Bipolar technology achieved by utilizing raised source and drain epitaxy. Standard processing steps are used from the CMOS process to achieved the device. Following the process depicted below, the standard nWell/Deep-nWell implant is used to dope the underlying silicon. Step 2 utilizes the nitride protection liner to open the area in the bipolar for the p-type epitaxy. Step 3 removal of material creating the trench in pFET devices and silicon in bipolar regions. Step 4 epitaxy of p-type such as SiGe insitu boron doped. Steps 5,6,and 7 are the same process just with the nFET regions with epitaxy of n-type such as SiC insitu phosphorus doped. The standard process ensues for CMOS to create contacts and the BEOL.

Step1, Start with deep n well implant on p type bulk or SOI wafer

Step2, CMOS gate stack, etch, and spacer deposition

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Step3, pFET spacer etch and recess source/drain areas

Step4, eSiGe epi for pFET

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Step5, pFET spacer dep and pattening

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Step6, Using mild selective etching to recess nFET source/drain and HBT area

Step7, eSiC epi for nFET source/drain and HBT area

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