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Improving the Bevel Edge RIE Process for wafer centricity on RIE tool by using DBS recipe

IP.com Disclosure Number: IPCOM000231101D
Publication Date: 2013-Sep-26
Document File: 4 page(s) / 239K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to base the whole Bevel Edge plasma etching on how well centered the wafer is placed on the Reactive Ion Etching (RIE) tool, and ensure that the F5 measurement tool provides a reliable recipe with repeatable data back to the RIE tool, while simultaneously monitoring the wafer centrality on F5 tools.

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Improving the Bevel Edge RIE Process for wafer centricity on RIE tool by using DBS recipe

The Reactive Ion Etching (RIE) tool is doing Pre and Post measurement on F5 to do wafer centrality for bevel edge plasma etching. The goal for the bevel edge (RIE tool) is to remove the film from the edge by using concentric circle measurements of F5 outputs at pre (after film deposition). Then, the tool goes back to F5 to obtain the post thk (after RIE plasma etches) and feedback delta for the RIE tool. This helps the RIE tool to adjust centrality to have consistent etching.

Current measurements done on F5 are based on the SE subsystem, which occasionally fails close to edge (e.g., 0.6 and 0.4) and needs SE optics alignment in case of F5 tool issues. No standard procedure exists to control and highlight F5 tool issues if the tool is off center. A solution is needed to address alignment issues at the edge of the wafer (e.g., 0.6 mm and 0.4mm from the edge) as well as track the F5 tool wafer placement.

The goal is to base the whole Bevel Edge plasma etching is on how well centered the wafer is placed on the RIE tool, and ensure that the F5 measurement tool provides a reliable recipe with repeatable data back to the RIE tool, while simultaneously monitoring the wafer centrality on F5 tools.

The steps for the core idea follow:


1. Test DBS sub system on the tool

2. Run repeatability tests on both SE and DBS systems to analyze improvement outside 1mm from the edge of the wafer

3....