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Trench DRAM with FinFET/nanowire access transistor and method of formation

IP.com Disclosure Number: IPCOM000231566D
Publication Date: 2013-Oct-07
Document File: 4 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to integrate embedded Dynamic Random Access Memory (eDRAM) with Fin Field Effect Transistor (FinFET) access transistors. The method is to use a Silicon on Insulator (SOI) wafer with pre-built trenches, in order to simplify as well as extend the capability of the process.

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Trench DRAM with FinFET/nanowire access transistor and method of formation

Integration of embedded Dynamic Random Access Memory (eDRAM) with Fin Field Effect Transistor (FinFET) access transistors is a challenge. In particular, because the cross section of the Fin landing next to the trench is very small, it is difficult to form the strap.

The solution is to use a Silicon on Insulator (SOI) wafer with pre-built trenches, eliminating the need to cut the Fin to form the trench. With the Fin overhanging the trench formation of the strap by the raised source/drain (RSD), epitaxial growth becomes significantly simplified. In addition, when the trench is pre-built it is not limited to a portion of the cell footprint directly next to S/D. It can extend laterally to increase the capacitance area.

The components and process for implementing the solution in a preferred embodiment follow:


1. Start with an SOI wafer with pre-built trenches (Figure 1)

Figure 1: SOI wafer with pre-built trenches

2. Fins are then formed, followed by standard process to form and pattern the gate stack, spacers, and optional S/D implants (Figures 2a and b).

Figure 2a: Cross section in S/D

1


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Figure 2b: Cross section in gate

3. An opening is made into the BOX to access the trench. The etch only etches the oxide and not the Si fin (Figure 3), so that the fin overhangs the opening.

Figure 3: Etch the trench in the BOX

2


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4. If desired, isotropic oxide etch is performed (i.e....