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Method and Apparatus for Network Tuning Via Configurable Device Input Parametrics

IP.com Disclosure Number: IPCOM000231833D
Publication Date: 2013-Oct-08
Document File: 3 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method in the area of memory devices to optimize signalling by sharing capacitance on signal inputs

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Method and Apparatus for Network Tuning Via Configurable Device Input Parametrics

On a memory card PCB, for example a JEDEC-approved RDIMM, the Command/Address and Clock signals to go to many DRAMs. Similarly, a system board PCB design may connect several DIMMs to the Command/Address and Clock signals. Although the lowest possible input capacitance is desirable to make it easier to drive, some times one has to "pad" signals by adding additional capacitance on DRAM, near the driver to slow it down and balance it against the DRAMs which are at the far end of the network.

    The proposal is to have "programmable input capacitance" for the purpose of balancing the network for devices at both near and far ends. The idea is to use the internal resources (mainly capacitors) and share them across the network, switching them in and out as needed.

Method:

The proposal is to use a mode register to turn on various capacitance values on the CMD/ADD/Clock signals it would make it easy to close the set-up and hold timing margins on the card.


It could be done many ways, they could be programmed based on their location on the card

once with MRS or they could be actively changed to different values for READ or WRITE in combination with other DRAMs like the ODT does for termination (see Figure 1).


The capacitors may need to be dynamically switched in and out based on the cycle, for

example when reading a DRAM at the end of the net, one may want to turn off all the added cap, but when readi...