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A Method and System for Detecting Cracks in Bonded Wafers

IP.com Disclosure Number: IPCOM000231885D
Publication Date: 2013-Oct-11
Document File: 4 page(s) / 67K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for implementing one or more wiring levels and/or chains between different wafers of a bonded stack. The one or more wiring levels are interconnected through one or more Through-Silicon Vias (TSVs) to form one or more crack sensor circuits for detecting cracks in the bonded stack.

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Page 01 of 4

A Method and System for Detecting Cracks in Bonded Wafers

Operations performed on a bonded wafer such as, but not limited to, edge trimming and dicing, can make the bonded wafer susceptible to cracking. Figure 1 illustrates the state of a bonded wafer, before and after operations, such as edge trimming.

Figure 1

In certain cases, the bonded wafer can be incorporated within a wafer stack. If cracks in the bonded wafer in the wafer stack remain undetected, the wafer stack could become unusable.

Disclosed is a method and system for using one or more Through-Silicon Vias (TSVs) for detecting cracks in the bonded wafer. The bonded wafer includes a top wafer and a bottom wafer. A TSV of the one or more TSVs can used to connect the top wafer to the bottom wafer. The top wafer and the bottom wafer can be tested for the presence of cracks using one or more test pads. The one or more test pads can be connected to crack sensing circuits implemented as one or more wiring levels made from a suitable material such as Copper. The one or more wiring levels can be positioned within, above or below, one or more of, the top wafer and the bottom wafer. Interconnects between the one or more wiring levels can be made using the one or more TSVs.

Figure 2 illustrates using the one or more TSVs to connect the top wafer to the bottom wafer.

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Page 02 of 4

Figure 2

In an implementation, a wiring level can be implemented as a bottom wafer chip ring placed within the bottom wafer as shown i...