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Tiled Sensor Array for High Performance Volumetric Image Capture

IP.com Disclosure Number: IPCOM000231955D
Publication Date: 2013-Oct-18
Document File: 5 page(s) / 135K

Publishing Venue

The IP.com Prior Art Database

Abstract

A curved or circular scan path (e.g., arcuate, nonlinear scan path) used for CT imaging systems (e.g., CBCT) can be more space efficient if the detector shape conformed to the scan path, e.g., a curved detector with a radius approaching that of the scan path would sweep out less volume than a flat detector. Certain scan systems can address space constrained applications including but not limited to extremity orthopedic applications, surgical applications or the like.

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Tiled Sensor Array for High Performance Volumetric Image Capture

High image capture frame rates with very good DQE at low exposure are highly desired for cone beam CT applications. Amorphous silicon flat panel detectors are limited in their capability to deliver this performance, but are cost effective for large image areas. CMOS detectors can deliver very high performance but are limited in active area to available wafer sizes.  Tiled detector arrays can be delivered with large active areas, but at high cost and with concerns on image uniformity and artifacts.  A scanned (CBCT) system can relax the constraints on the allowable tile gaps/positioning.

A curved or circular scan path (e.g., arcuate, nonlinear scan path) used for CT imaging systems (e.g., CBCT) can be more space efficient if the detector shape conformed to the scan path, e.g., a curved detector with a radius approaching that of the scan path would sweep out less volume than a flat detector.  Exemplary embodiments can address space constrained applications including but not limited to extremity orthopedic applications, surgical applications or the like.

Exemplary detector assemblies can arrange a plurality or an array of flat CMOS or amorphous silicon detector tiles to be integrated into an advantaged CBCT capture system.

Figure 1 shows a scan system with a standard flat panel detector.

Figure 2 shows a scan system with tiled flat panel detectors.

Figure 3 shows tiled FPDs that are offset vertically and/or horizontally to decrease the impact of gaps between tiled FPDs, which can be compensated for by interpolation techniques during reconstruction. In Figure 3, a dotted line shows projected imaging area. 

Figure 4

Figure 4 shows a standard amorphous silicon DR detector.

Figure 5

Figure 5 shows a tiled amorphous silicon arrangement (e.g., using standard amorphous silicon DR detector).  As shown in Figure 5, readout electronics on edge of sensor panel can be “concealed” by overlap with front detector.  Further, a slight offset in capture plane of each sensor panel can be corrected through calibration.

Figure 6

Figure 6 shows certain scan systems with tiled flat panel detectors can reduce thickness t of volume swept by tiled detector by at least 10% smaller, 20% smaller, 50% smaller, etc..

In certain scan systems, geometric calibration/interpolation algorithms can correct for tiling related errors and inter-panel gaps.  For example, various image reconstruction algorithms can be generated for this capture geometry.  The effectiveness of the interpolation is enhanced by the fact that the detector active sensing area moves over the former gap locations during the gantry rotation thus providing actual capture data in the areas formerly in the gap between sensors.

In certain scan systems, characterization and correction of panel segment non-uniformities can be across multiple devi...