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Intuitive Spare Cell Selection for Effective ECOs

IP.com Disclosure Number: IPCOM000232127D
Publication Date: 2013-Oct-18
Document File: 5 page(s) / 807K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for selecting spare cell modules for an IC design uses standard cells having generic universal gates (NAND, NOR, etc.) as part of the spare module. Spare cell components are selected dynamically depending on logical contours implemented in small, physical sub-segments of the design.

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Intuitive Spare Cell Selection for Effective ECOs

Abstract.

A method for selecting spare cell modules for an IC design uses standard cells having generic universal gates (NAND, NOR, etc.) as part of the spare module.  Spare cell components are selected dynamically depending on logical contours implemented in small, physical sub-segments of the design.

Introduction

Due to the increase in design complexity and the need to reduce time to market, more and more bugs escape pre-silicon validation and are found in post-silicon, forcing designers to realize the fixes through additional tape-out. Also with the shrinking geometries, these design re-spins are becoming very costly.

A mask set includes multiple individual masks, whose costs vary depending on their minimal feature sizes. Since transistor masks exhibit the smallest feature size, they are the most expensive, while metal layers have larger features and are relatively cheaper.  Therefore, re-spin costs can be reduced by re-using transistor masks and modifying only the metal masks.  Thus, spare cells are added in the initial design and then later are used in ECO’s to fix the bugs seen in post-silicon validation. However it is impractical to perform ECO if the spare logic added to the design is not conducive to achieve the missing functionality.

Current Methodology for Selecting Spare Cells.

The most commonly used spare cell methodology employs a generic spare module having universal gates (NAND, NOR, etc.). This generic module is added all over the design, oblivious to the properties of the local logic blocks and irrespective of the designs local requirements.  Thus, a lot of ECOs are rejected due to unavailability of the correct logic in Spare Cells/Modules or implemented with higher cost.

For example, cores performing FFT or implementing mathematical functions need specific adders, comparators, XOR cells, etc., while feed through modules need repeaters rather than generic logic.

The absence of these specific cells at the correct locations renders many ECO’s ineffective for design in terms of functionality to be implemented and timing. Figure 1 shows the trade-offs to achieve complex functionality using universal gates.

Functionality

Universal Gates Required

XOR

4 NAND

Full Adder

7 NAND /  (2 XOR + 2 AND + 1 OR)

Half Adder

5 NAND

MUX

4 NAND

Fig1: Complex gates using universal gates.

New Approach for Spare Cell Selection: Intuitive Spares

The new approach is to add location aware intuitive spare logic rather than a generic spare cell module being added to all the physical segments in the entire design.

With the proposed solution:

·         The entire design is sub-divided into multiple, smaller physical segments.

·         The logic used in these segments is analyzed.

·         Depending on the results, the most common logic in a segment is picked to be part of the spare cells catering to this physical segment.

Figure 2 represents a typical modern day design. The design is divided into small regions of 200...