Browse Prior Art Database

Low Power High Voltage recovery circuit with reverse current protection

IP.com Disclosure Number: IPCOM000232635D
Publication Date: 2013-Nov-22
Document File: 3 page(s) / 421K

Publishing Venue

The IP.com Prior Art Database

Abstract

Non Volatile Memory (NVM) in general and Flash memory in particular perform ERASE/PROGRAM operations exposing bit cells to High Voltages (HV) supplies generated on chip by Charge Pumps (CP), however, during READ operation the same bit cell is exposed to a much lower voltage. The transition operation between HV and lower supplies needs to be controlled in order to avoid high IHS (Hot Switch Current) currents. Hereafter is presented a circuit which is both precise and low cost solution to solve the recovery voltage procedure in a monolithic environment.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 35% of the total text.

Low Power High Voltage recovery circuit with reverse current protection

Abstract—Non Volatile Memory (NVM) in general and Flash memory in particular perform ERASE/PROGRAM operations exposing bit cells to   High Voltages (HV) supplies generated on chip by Charge Pumps (CP), however, during READ operation the same bit cell is exposed to a much lower voltage. The transition operation between HV and lower supplies needs to be controlled in order to avoid high IHS (Hot Switch Current) currents. Hereafter is presented a circuit which is both precise and low cost solution to solve the recovery voltage procedure in a monolithic environment.

                                                                                                                                                                 I.          Introduction

The recovery voltage procedure includes switching from a HV domain to a lower voltage domain or vice versa, with a controlled current flowing through the components, and under voltage conditions defined by components Safe Operating Area (SOA). Usually the circuit which performs this functionality is an Operational Transconductance Amplifier (OTA) block as shown in Fig. 2.

The IHS, illustrated in Fig. 1, represents a current which is flowing in an uncontrollable way that can shorten component lifetime. Usually, production tests are not designed to detect this sort of failure.  Instead, the failure eventually appears in the field increasing costs with re[MJB1] ?? spins at the SOC level and silicon debug.

Fig. 1. Illustration of Voltage Recovery strategies.

In the literature there are several strategies to switch between voltage domains. Fig. 2 shows one based on an OTA block which is supposed to bring down a high voltage to a lower voltage.

The Logic control generates EN_sw signal which selects the PATH net voltage connection.

When EN_sw asserted to “0” the Supply Voltage VDD is selected. When EN_sw asserted to “1” the controllable recovery voltage is selected.

During read operation the Supply voltage is applied at M0 gate and the wordline assumes regulated Vddf voltage (2.8V).  

The PATH net assumes an external Supply Voltage VDD when required.

Fig. 2. OTA based Recovery voltage strategy.

To have bit cell gate reaching Vddf voltage in a reasonable time, the NMOS M0 device threshold voltage (Vth0) imposes limits to the minimum VDD voltage. In a first order approximation, the gate voltage reaching the bit cells is given by VDD-Vddf-Vth0. The smaller the result of this expression is, the slower the response of M0 will be, due to M0 IDS current (Eq. 1 section II), generated by VGS voltage available. However, VDD range is a requirement driven by application, in some embodiments VDD specification may drop under 2.5V.

Due to aggressive VDD requirement demanded by modern applications, a charge pump can be added to this system to drive M0 gate. The charge pump is required if VDD approaches Vddf+Vth0 in order to establish a minimum speed to M0 to convey Vddf to bit cell gate.

The charge pump is turned OFF during PROGRAM or ERASE operation. See Fig.  3.

If the voltage on PATH net is above VDD vo...