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A Method Of Accumulating Multiple Transactions Into A Single Packet To Improve Hardware Co-Simulation Of SOC System

IP.com Disclosure Number: IPCOM000233806D
Publication Date: 2013-Dec-23
Document File: 8 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

This disclosure describe A Method Of Accumulating Multiple Transactions Into A Single Packet To Improve Hardware Co-Simulation Of SOC System

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 10% of the total text.

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FPGA-In-the-Loop, Co-simulation framework of SystemC SoC Virtual Prototype and Custom Logic

ABSTRACT

To address the increasing demand of System-on-Chip (SoC) for high performance applications and IP programmability, a number of chips have been developed with hardened SoC and FPGA devices in a single-chip. Like any other SoC platforms, early software development before hardware availability using a Virtual Prototype (VP) is essential. However, the existent RTL for custom logic makes it non-trivial to simulate the entire system with software models written in high-level language (i.e. SystemC/C/C++). In this paper, we describe our unique virtual prototyping framework called "FPGA-In-the-Loop (FIL)" to enable co-simulation of software models in VP and custom logics running in FPGA in its native speed. This platform enables user to start early software development and integration of the entire hardware platform without a need to develop software models for custom logics. More importantly, we have overcome two biggest challenges in such co-simulation system; 1) communication channel performance bottleneck and 2) software-visible asynchronous signal timing correctness (i.e. interrupt). Our framework was able 1) to optimize communication between VP and FPGA to achieve up to 872 Mbps effective throughput, the highest reported in our knowledge and 2) to guarantee software- visible asynchronous signal delivery timing (i.e. interrupt) between the two simulation domains. Finally, we implemented our framework on a real hybrid platform with hardened SoC and FPGA to demonstrate the complete embedded Linux stack running with custom video/touchscreen IPs in FPGA.

Categories and Subject Descriptors

B.1.2 [Hardware]: Control Structures and Microprogramming - simulation

General Terms

Algorithms, Design, Experimentation, Measurement, Performance, Verification and Standardization

Keywords

Virtual Platform, Virtual Prototype, SystemC, TLM, Custom Logic, FPGA, SoC, Embedded Software and Co-simulation


1.INTRODUCTION

  Owing to semiconductor process technology advancement and success of feature-rich consumer electronics, today's SoC designs have the highest software demand in history. Many of today's System-on-Chip (SoC) devices are not designed solely to serve any single or particular set of applications, but rather to leverage system software / hardware combinations to adapt to continuously evolving user needs. This trend is pushing system and SoC vendors to deliver more and more software content, including device drivers, full board support packages for supported operating systems, and application enablers such as middleware and Android. At the 90nm technology node, software effort has already surpassed the hardware effort in a typical SoC project and it is increasing, becoming the gating factor for time-to-market as shown in Figure 1 [13].

  This trend is getting more prominent with SoC platform with custom logics. Software contents that run on such plat...