Browse Prior Art Database

ASIC Bit error-rate (BER) Checker

IP.com Disclosure Number: IPCOM000233807D
Publication Date: 2013-Dec-23
Document File: 7 page(s) / 692K

Publishing Venue

The IP.com Prior Art Database

Abstract

This disclosure describe ASIC Bit error-rate (BER) Checker

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 7

ON-CHIP BER ARCHITECTURE FOR HIGHSPEED TRANSCEIVERS

© 2012 Altera Corporation-Confidential


Page 02 of 7

Outline


BER checker is a component of Eye monitor


(Previous) Bit checker issues


New bit checker architecture


Control scheme


Position selection



Page 03 of 7

Eye monitor overview

3


Page 04 of 7

(Previous) Bit checker issues

Error not accurate

Can be optimized

Nbit adder needed in upper level

Reset should be handled carefully

Async counter may violate timing at higher speed

4


Page 05 of 7

New bit checker architecture


Cycle counter is 48bit


Enough for test 0.5E-15 BER (1 cycle == 2 UI)


When error counter saturate, it'll stop cycle counter automatically


Register IF between BER checker and upper logic


Page 06 of 7

Control scheme



Page 07 of 7

Position selection


For each PI code, there're one or two "good position" (sel_2nd can be 1/0)


Correlation between "PI code change" and "selection change"


May just need to check two position