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An Automatic Stub based Self-learning Simulation Method for Verification Speed-up and Quality Enhancement Disclosure Number: IPCOM000233968D
Publication Date: 2014-Jan-06
Document File: 5 page(s) / 73K

Publishing Venue

The Prior Art Database


This disclosure proposed an automatic stub based self-learning and dynamic module loading simulation method. Within this disclosure, while SOC verification, stub modules are automatically generated with user defined attributes for the dedicated modules. Simulator could link either real design model or stub models together to complete whole simulation work based on pre-defined model list or self-learning result. The proposed method can fully take advantage of SOC hierarchy methodology, speeds up simulation time while reduce the CPU/Memory resource.

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An Automatic Stub based Self

An Automatic Stub based Self-

learning Simulation Method for Verification Speed- --learning Simulation Method for Verification Speed

learning Simulation Method for Verification Speed

--up and Quality Enhancement

up and Quality Enhancement

With the fast increasing complexity of integrated circuits, verification has become the bottleneck of today's SOC design flow. In fact, over 70% of the SOC design turn-around time is spent on the verification process in a typical SOC design project. Among

various verification tasks, Register Transfer Level (RTL) simulation is the most widely used method to validate the correctness of digital SOC designs. When simulating a large SOC design with complicated internal behaviors (e.g., CPU cores running embedded software), digital SOC simulation can be extremely time consuming. Particularly, netlist simulation will consume more than 10 times of simulation time compared with RTL simulation. Since RTL-to-layout is still the most prevalent SOC design methodology, it is essential to speed-up the Digital Logic simulation process.

Some simulator accelerating methods are listed as below:

(1) Chen proposes an architecture driven partitioning algorithm for netlist with multi terminal nets. The target architecture was a multi field-programmable gate array (FPGA).

The goals of the algorithm are to minimize the number of FPGA chips used and to maximize routability [1].

(2) Li uses a module-based simulation mapping method. Although the details of the algorithm are not described in the paper, the author states that it reduces the communication
cost and achieves a better load balancing

(3) Chang uses the module tree as the data structure instead of the circuit hypergraph . Modules are not moved by the algorithm. Nor does it use an iterative improvement technique. The author does not mention the cut-size achieved by the algorithm and concludes that the algorithm achieves better performance then a sequential simulation and is efficient [3].

(4) Cherng proposes a module migration based partitioning algorithm which tends to keep the cluster intact in order to reduce the net cut size. The algorithm implicitly promotes the move of clusters of modules during the module migration process by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Load balancing was not considered in this algorithm[4].

(5) Qian introduces a methodology to translate Verilog RTL description into equivalent GPU source code so as tosimulate circuit behavior on GPUs. In addition, a CMB based
parallel simulation protocol is also adopted to provide a
sufficient level of parallelism. Because RTL simulation lacks data level parallelism, this disclosure also presents a novel solution to useGPU as an efficient task-level parallel processor. Experimental results prove that this GPU based simulator ou...