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Method and structure to detect epitaxial merge during source drain epitaxy

IP.com Disclosure Number: IPCOM000233996D
Publication Date: 2014-Jan-06
Document File: 5 page(s) / 3M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure that allows detecting epitaxial merge and detecting the progress of epitaxial merge.

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Method and structure to detect epitaxial merge during source drain epitaxy

Fin Field Effect Transistor (FinFET) technology employs epitaxial processing to merge fins in the source/drain regions. Alternate unmerged fins are also considered a main option, especially in bulk integration. Both options have the common purpose to increase the area available to create a contact. In addition, the in-situ doping of the epitaxy (epi) is used to drive in dopants to form the junction . Un-merged epitaxy is very challenging, since the space between the fins is very tight (fin pitch 40 or 45 nm). The desired gap after epitaxy in between the un-merged fins with epi-diamond is 1-2 nm.

Accidental fin merge is likely, if pitch walking, fin erosion, or epi deposition times are of specification. Having some of the fins merged, but the bulk (i.e. 90%) unmerged is not desirable. In the unmerged integration scheme, none of the fins should be merged. Detecting unwanted merge is very extensive (top down scanning electron microscopy review of whole wafer) if not impossible with the characterization tools available.

Possible short between neighboring fins because of lateral epi growth is a concern for dense Static Random Access Memory (SRAM) and enhanced Dynamic Random

Access Memory (eDRAM). Fin spacing is roughly 50nm in the most aggressive case. The present blanket fin epi short monitor overestimates the severity of problem due to epi loading effect.

A method is needed to evaluate fin isolation in a realistic environment that resembles Polysilicon Con...